CS152 Computer Architecture and Engineering Lecture 17 Buses and Networks 2004 10 26 John Lazzaro www cs berkeley edu lazzaro Dave Patterson www cs berkeley edu patterson www inst eecs berkeley edu cs152 CS 152 L17 Buses Networks 1 Fall 2004 UC Regents Review Synchronous DRAM flexible bus protocol for array access VM Uniform memory models protection sharing A TLB acts as a fast cache for recent address translations Operating systems manage the page table and often the TLB CS 152 L17 Buses Networks 2 Fall 2004 UC Regents Outline Buses Networks Buses Networks CS 152 L17 Buses Networks 3 Fall 2004 UC Regents What is a A Busbus Is shared communication link single set of wires used to connect multiple subsystems Processor Input Control Memory Datapath Output A Bus is also a fundamental tool for composing large complex systems systematic means of abstraction CS 152 L17 Buses Networks 4 Fall 2004 UC Regents Buses PCI CS 152 L17 Buses Networks 5 Fall 2004 UC Regents Advantages of Buses I O Device Processer I O Device I O Device Memory Versatility New devices can be added easily Peripherals can be moved between computer systems that use the same bus standard Low Cost A single set of wires is shared in multiple ways CS 152 L17 Buses Networks 6 Fall 2004 UC Regents Disadvantage of Buses I O Device I O Device I O Device Processer Memory It creates a communication bottleneck The bandwidth of that bus can limit the maximum I O throughput The maximum bus speed is largely limited by The length of the bus The number of devices on the bus The need to support a range of devices with Widely varying latencies Widely varying data transfer rates CS 152 L17 Buses Networks 7 Fall 2004 UC Regents The General Organization of a Bus Control Lines Data Lines Control lines Signal requests and acknowledgments Indicate what type of information is on the data lines Data lines carry information between the source and the destination Data and Addresses Complex commands CS 152 L17 Buses Networks 8 Fall 2004 UC Regents Master versus Slave Master issues command Bus Master Bus Slave Data can go either way A bus transaction includes two parts Issuing the command and address Transferring the data request action Master is the one who starts the bus transaction by issuing the command and address Slave is the one who responds to the address by Sending data to the master if the master ask for data Receiving data from the master if the master wants to send data CS 152 L17 Buses Networks 9 Fall 2004 UC Regents Types of Processor Memory Bus design specific Buses Short and high speed Only need to match the memory system Maximize memory to processor bandwidth Connects directly to the processor Optimized for cache block transfers I O Bus industry standard Usually is lengthy and slower Need to match a wide range of I O devices Connects to the processor memory bus or backplane bus Backplane Bus standard or proprietary Backplane an interconnection structure within the chassis Allow processors memory and I O devices to coexist Cost advantage one bus for all components CS 152 L17 Buses Networks 10 Fall 2004 UC Regents What defines a bus Transaction Protocol Timing and Signaling Specification Wires Electrical Specification Physical Mechanical Characterisics the connectors CS 152 L17 Buses Networks 11 Fall 2004 UC Regents Administrivia HW 3 Lab 4 Homework 3 due 10 26 Tuesday 283 Soda in CS 152 box at 5 PM Lab 4 is next Plan by Thur for TA CS 152 L17 Buses Networks 12 Fall 2004 UC Regents Main components of Intel Chipset Pentium III Northbridge a DMA controller connecting the processor to memory the AGP graphic bus and the south bridge chip Southbridge I O PCI bus Disk controllers USB controlers Audio Serial I O Interrupt controller Timers CS 152 L17 Buses Networks 13 Fall 2004 UC Regents What is DMA Direct Memory Typical I O devices Access must transfer large amounts of data to memory of processor Disk must transfer complete block Large packets from network Regions of frame buffer DMA gives external device ability to access memory directly much lower overhead than having processor request one word at a time Issue Cache coherence What if I O devices write data that is currently in processor Cache The processor may never see new data Solutions Flush cache on every I O operation expensive Have hardware invalidate cache lines remember Coherence cache misses CS 152 L17 Buses Networks 14 Fall 2004 UC Regents Main components of Intel Chipset Pentium 4 System Bus Front Side Bus 64 bits x 400 533 800 MHz Gbit Ethernet 125 MB s Hub bus 8 bits x 266 MHz 2 Serial ATA 150 MB s 10 100 Mbit Ethernet 1 25 12 5 MB s Parallel ATA 100 MB s 8 USB 60 MB s 1 PCI 32b x 33 MHz CS 152 L17 Buses Networks 15 Fall 2004 UC Regents I O Chip Sets Customize Processor to App 875P Chip set Target Segment System Bus 64 bit 845GL Chip set Performance PC Value PC 800 533 MHz 400 MHz Memory Controller Hub North bridge Package size pins 42 5 x 42 5 mm 1005 37 5 x 37 5 mm 760 Memory Speed DDR 400 333 266 SDRAM DDR 266 200 PC133 SDRAM Memory buses widths 2 x 72 1 x 64 Maximum Memory Capacity 4 GB 2 GB Memory Error Correction available Yes No AGP Graphics Bus Speed Yes 8X or 4X No Graphics controller External Internal Extreme Graphics CSA Gigabit Ethernet interface Yes No South bridge interface speed 8 bit 266 MHz 266 MHz I O Controller Hub South bridge Package size pins 31 x 31 mm 460 31 x 31 mm 421 PCI bus width speed masters 32 bit 33 MHz 6 masters 32 bit 33 MHz 6 masters Ethernet MAC controller interface 100 10 Mbit 100 10 Mbit USB 2 0 ports controllers 8 4 6 3 ATA 100 ports 2 2 Serial ATA 150 controller ports Yes 2 No RAID 0 controller Yes No AC 97 audio controller interface Yes Yes I O management SMbus 2 0 GPIO SMbus 2 0 GPIO CS 152 L17 Buses Networks 16 Fall 2004 UC Regents Networks Networks are major medium used to communicate between computers Key characteristics of typical networks Distance 0 01 to 10 000 kilometers Local Area Network LAN 1 km vs Wide Area Network WAN to 10000 km Speed 0 001 MB sec to 100 MB sec Topology Bus ring star tree Shared lines None switched point topoint or shared multidrop CS 152 L17 Buses Networks 17 Fall 2004 UC Regents Protocols HW SW Interface Internetworking allows computers on independent and incompatible networks to communicate reliably and efficiently Enabling technologies SW standards that allow reliable communications without reliable networks Hierarchy of SW layers giving each layer responsibility for portion of overall
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