Slide 1ReviewOutlineWhat is a bus?Buses: PCIAdvantages of BusesDisadvantage of BusesThe General Organization of a BusMaster versus SlaveTypes of BusesWhat defines a bus?Administrivia - HW 3, Lab 4Main components of Intel Chipset: Pentium IIIWhat is DMA (Direct Memory Access)?Main components of Intel Chipset: Pentium 4I/O Chip Sets Customize Processor to AppNetworksProtocols: HW/SW InterfaceProtocolHourglass Architecture of InternetWhy the Hourglass Architecture?TCP/IP packetLong Haul Networks (or WANs)Connecting NetworksLocal Area Networks: EthernetNetwork MediaOptical Jitter from SF to Washington DC, 2001Busses in TransitionSerial successors of Parallel I/O BussesATA cablesSummaryCS 152 L17 Buses & Networks (1)Fall 2004 © UC RegentsCS152 – Computer Architecture andEngineeringLecture 17 – Buses and Networks 2004-10-26John Lazzaro(www.cs.berkeley.edu/~lazzaro)Dave Patterson (www.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs152/CS 152 L17 Buses & Networks (2)Fall 2004 © UC RegentsReviewVM: Uniform memory models,protection, sharing.Synchronous DRAM: flexiblebus protocol for array accessOperating systems manage the page table and (often) the TLBA TLB acts as a fast cache forrecent address translations.CS 152 L17 Buses & Networks (3)Fall 2004 © UC RegentsOutline•Buses•Networks•Buses => NetworksCS 152 L17 Buses & Networks (4)Fall 2004 © UC RegentsA Bus Is:•shared communication link•single set of wires used to connect multiple subsystems•A Bus is also a fundamental tool for composing large, complex systems–systematic means of abstractionControlDatapathMemoryProcessorInputOutputWhat is a bus?CS 152 L17 Buses & Networks (5)Fall 2004 © UC RegentsBuses: PCICS 152 L17 Buses & Networks (6)Fall 2004 © UC Regents•Versatility:–New devices can be added easily–Peripherals can be moved between computersystems that use the same bus standard•Low Cost:–A single set of wires is shared in multiple waysMemoryProcesserI/O Device I/O Device I/O DeviceAdvantages of BusesCS 152 L17 Buses & Networks (7)Fall 2004 © UC Regents•It creates a communication bottleneck–The bandwidth of that bus can limit the maximum I/O throughput•The maximum bus speed is largely limited by:–The length of the bus–The number of devices on the bus–The need to support a range of devices with:•Widely varying latencies •Widely varying data transfer ratesMemoryProcesserI/O Device I/O Device I/O DeviceDisadvantage of BusesCS 152 L17 Buses & Networks (8)Fall 2004 © UC Regents•Control lines:–Signal requests and acknowledgments–Indicate what type of information is on the data lines•Data lines carry information between the source and the destination:–Data and Addresses–Complex commandsData LinesControl LinesThe General Organization of a BusCS 152 L17 Buses & Networks (9)Fall 2004 © UC Regents•A bus transaction includes two parts:–Issuing the command (and address) – request–Transferring the data – action•Master is the one who starts the bus transaction by:–issuing the command (and address)•Slave is the one who responds to the address by:–Sending data to the master if the master ask for data–Receiving data from the master if the master wants to send dataBusMasterBusSlaveMaster issues commandData can go either wayMaster versus SlaveCS 152 L17 Buses & Networks (10)Fall 2004 © UC RegentsTypes of Buses•Processor-Memory Bus (design specific)–Short and high speed–Only need to match the memory system•Maximize memory-to-processor bandwidth–Connects directly to the processor–Optimized for cache block transfers•I/O Bus (industry standard)–Usually is lengthy and slower–Need to match a wide range of I/O devices–Connects to the processor-memory bus or backplane bus•Backplane Bus (standard or proprietary)–Backplane: an interconnection structure within the chassis–Allow processors, memory, and I/O devices to coexist–Cost advantage: one bus for all componentsCS 152 L17 Buses & Networks (11)Fall 2004 © UC RegentsWiresPhysical / Mechanical Characterisics – the connectorsElectrical SpecificationTiming and Signaling SpecificationTransaction ProtocolWhat defines a bus?CS 152 L17 Buses & Networks (12)Fall 2004 © UC RegentsAdministrivia - HW 3, Lab 4Homework 3 due 10/26 (Tuesday),283 Soda, in CS 152 box at 5 PMLab 4 is next: Plan by Thur for TACS 152 L17 Buses & Networks (13)Fall 2004 © UC RegentsMain components of Intel Chipset: Pentium III•Northbridge: a DMA controller, connecting the processor to memory, the AGP graphic bus, and the south bridge chip•Southbridge : I/O–PCI bus–Disk controllers–USB controlers–Audio–Serial I/O–Interrupt controller–TimersCS 152 L17 Buses & Networks (14)Fall 2004 © UC RegentsWhat is DMA (Direct Memory Access)?•Typical I/O devices must transfer large amounts of data to memory of processor:–Disk must transfer complete block –Large packets from network–Regions of frame buffer•DMA gives external device ability to access memory directly: much lower overhead than having processor request one word at a time.•Issue: Cache coherence:–What if I/O devices write data that is currently in processor Cache? •The processor may never see new data!–Solutions: •Flush cache on every I/O operation (expensive)•Have hardware invalidate cache lines (remember “Coherence” cache misses?)CS 152 L17 Buses & Networks (15)Fall 2004 © UC RegentsMain components of Intel Chipset: Pentium 4•System Bus (“Front Side Bus”): 64 bits x 400, 533, 800 MHz•Gbit Ethernet: 125 MB/s•Hub bus: 8 bits x 266 MHz•2 Serial ATA: 150 MB/s•10/100 Mbit Ethernet:1.25 - 12.5 MB/s•Parallel ATA:100 MB/s•8 USB: 60 MB/s•1 PCI: 32b x 33 MHzCS 152 L17 Buses & Networks (16)Fall 2004 © UC RegentsI/O Chip Sets Customize Processor to App875P Chip set 845GL Chip setTarget Segment Performance PC Value PCSystem Bus (64 bit) 800/533 MHz 400 MHzMemory Controller Hub (“North bridge”)Package size, pins 42.5 x 42.5 mm, 1005 37.5 x 37.5 mm, 760Memory Speed DDR 400/333/266 SDRAM DDR 266/200, PC133 SDRAMMemory buses, widths 2 x 72 1 x 64Maximum Memory Capacity 4 GB 2 GBMemory Error Correction available? Yes NoAGP Graphics Bus, Speed Yes, 8X or 4X NoGraphics controller External Internal (Extreme Graphics)CSA Gigabit Ethernet interface Yes NoSouth bridge interface speed (8 bit) 266 MHz 266 MHzI/O Controller Hub (“South bridge”)Package size, pins 31 x 31 mm,
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