CS 152 Computer Architecture and Engineering Lecture 2 Single Cycle Datapaths 2006 8 31 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 1 Single cycle CPU project 3 weeks Pipelined CPU 4 weeks Final Project 5 weeks IBM Power 5 die photo a die is an unpackaged part CS 152 L2 Single Cycle Datapaths supports a 1 875 Mbyte on chip L2 cache Power4 and Power4 systems both have 32Mbyte L3 caches whereas Power5 systems have a 36 Mbyte L3 cache Figure 2 Power5 chip FXU fixed point execution unit ISU instruction sequencing unit IDU instruction decode unit LSU load store unit IFU instruction fetch unit FPU floating point unit and MC memory controller W supp threa Proc ing uses T Powe two i two l the c tipro cores cach ident each with The slice t can i W chip Havi the p L2 m To r the inate nal c Last Time CS 152 Course Introduction Teams of 4 5 students UC Regents Fall 2006 UCB 2 Administrivia Upcoming deadlines Friday Teams meet the TAs 12 2 and 3 5 125 Cory 1 Decide on group names 2 Collect your NT usernames bring your account sheet Tuesday Lab 1 final report due 11 59 PM via the submit program I will be around all weekend long email lazzaro cs or phone 643 4005 for Cory access Check Accounts OK Cardkey woes Thursday 9 7 Lab 2 preliminary design document due to TAs via email 11 59 PM CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 3 CS 152 Real hardware not simulation Will we be fabricate CPU dies Back when I was taking classes 1984 Caltech our project course did fab chips Intel XScale 80200 used in earlier HP PocketPCs CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 4 Moore s Law for CPUs DRAMs Moore s Lawand 2005 Transistors Per Die 1010 1G 109 108 107 106 105 104 1K 103 102 101 2G 512M 256M 128M Itanium 2 Processor 64M Itanium Processor 16M Pentium 4 Processor 4M Pentium III Processor 1M Pentium II Processor 256K Pentium Processor 64K 486 Processor 16K 386 Processor 4K 80286 8080 8086 8008 1965 Data Moore 4004 Memory Microprocessor 100 1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 From Facing the Hot Chips Challenge Again Bill Holt Intel presented at Hot Chips 17 2005 Sourc e Intel CS 152 L2 Single Cycle Datapaths 4 UC Regents Fall 2006 UCB 5 Main driver device scaling Scaling The Fundamental Cost Driver 350nm 200mm 250nm 200mm Twice the circuitry in the same space architectural innovation 180nm 200mm OR 130nm 200mm The same circuitry in half the space cost reduction 90nm 300mm 65nm 300mm Dual Core Half the die size for the same capability than in the prior process From Facing the Hot Chips Challenge Again Bill Holt Intel presented at Hot Chips 17 2005 CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 6 Secondary driver Wafer size Processed Wafer Cost From Facing the Hot Chips Challenge Again Bill Holt Intel presented at Hot Chips 17 2005 CS 152 L2 Single Cycle Datapaths Wafer size conversions offset trend of increasing wafer processing cost UC Regents Fall 2006 UCB 7Sou Thus cost per transistor Moore s Law plummets 2005 Transistors Per Die 1010 1G 109 108 107 106 105 104 1K 103 102 101 2G 512M 256M 128M Itanium 2 Processor 64M Itanium Processor 16M Pentium 4 Processor 4M Pentium III Processor 1M Pentium II Processor 256K Pentium Processor 64K 486 Processor 16K 386 Processor 4K 80286 8080 8086 8008 1965 Data Moore 4004 Memory Microprocessor 100 1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 From Facing the Hot Chips Challenge Again Bill Holt Intel presented at Hot Chips 17 Sourc e Intel2005 CS 152 L2 Single Cycle Datapaths 4 UC Regents Fall 2006 UCB 8 Lab 2 A Single Cycle MIPS CPU CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 9 Today Single Cycle Datapath Design The book presentation of single cycle processors is sufficient to do Lab 2 This lecture is not This lecture is a gentle introduction to prepare you to read the book CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 10 Single cycle data paths Assumptions Processor uses synchronous logic design a clock 0 7 f T 1 MHz 1 s 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns 4 D All state elements act like positive edgetriggered flip flops CS 152 L2 Single Cycle Datapaths Q 5 5 0 Reset 0 clk UC Regents Fall 2006 UCB 11 Review Edge Triggered D Flip Flops D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle CLK D Q CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 12 Review Edge Triggering in Verilog D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle module ff D Q CLK CLK input D CLK output Q always CLK Q D Module code has two bugs Where endmodule CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 13 Review Edge Triggered D Flip Flops D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle module ff D Q CLK CLK input D CLK output Q reg Q always posedge CLK Q D endmodule CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 14 define Single cycle datapath 0 7 4 All instructions execute in a single cycle of the clock positive edge to 5 60 7 89 positive edge 5 0 7 8 Advantage a great way to learn CPUs CS 152 L2 Single Cycle Datapaths Drawbacks unrealistic 012 34 5 hardware assumptions slow clock period UC Regents Fall 2006 UCB 15 Recall MIPS R format instructions Syntax ADD 8 9 10 Semantics 8 9 10 Instruction Fetch Fetch next inst from memory 012A4020 Instruction Decode opcode rs rt rd shamt funct Decode fields to get ADD 8 9 10 Operand Fetch Execute Result Store Next Instruction Retrieve register values 9 10 Add 9 to 10 Place this sum in 8 Prepare to fetch instruction that follows the ADD in the program CS 152 L2 Single Cycle Datapaths UC Regents Fall 2006 UCB 16 Goal 1 An R format single cycle CPU Syntax ADD 8 9 10 opcode Sample ADD 8 SUB 4 AND 9 rs program 9 10 8 3 8 4 How registers get their initial values are not of concern to us right now CS 152 L2 Single Cycle Datapaths rt Semantics 8 9 10 rd shamt funct No branches or jumps machine only runs straight line code No loads or stores machine has no use for data memory only instruction memory UC Regents Fall 2006 UCB 17 Separate Read Only Instruction Memory Instr Mem 32 Data Reads are combinational Put …
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