CS 152 Computer Architecture and Engineering Lecture 7 Memory Hierarchy II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 February 9 2011 CS152 Spring 2011 Last time in Lecture 6 Dynamic RAM DRAM is main form of main memory storage in use today Holds values on small capacitors need refreshing hence dynamic Slow multi step access precharge read row read column Static RAM SRAM is faster but more expensive Used to build on chip memory for caches Cache holds small set of values in fast memory SRAM close to processor Need to develop search scheme to find values in cache and replacement policy to make space for newly accessed locations Caches exploit two forms of predictability in memory reference streams Temporal locality same location likely to be accessed again soon Spatial locality neighboring location likely to be accessed soon February 9 2011 CS152 Spring 2011 2 CPU Cache Interaction 5 stage pipeline 0x4 E Add M A nop PC addr inst IR D Decode Register Fetch ALU Y Primary Data rdata Cache hit wdata wdata B hit PCen Primary Instruction Cache MD1 we addr R MD2 Stall entire CPU on data cache miss To Memory Control Cache Refill Data from Lower Levels of Memory Hierarchy February 9 2011 CS152 Spring 2011 3 Improving Cache Performance Average memory access time Hit time Miss rate x Miss penalty To improve performance reduce the hit time reduce the miss rate reduce the miss penalty What is the simplest design strategy Biggest cache that doesn t increase hit time past 1 2 cycles approx 8 32KB in modern technology design issues more complex with out of order superscalar processors February 9 2011 CS152 Spring 2011 4 Serial versus Parallel Cache and Memory access is HIT RATIO Fraction of references in cache 1 is MISS RATIO Remaining references Addr Addr CACHE Processor Data Data tcache 1 tmem Average access time for serial search Addr CACHE Processor Data Main Memory Data Average access time for parallel search Main Memory tcache 1 tmem Savings are usually small tmem tcache hit ratio high High bandwidth required for memory path Complexity of handling parallel paths can slow tcache February 9 2011 CS152 Spring 2011 Causes for Cache Misses Compulsory first reference to a block a k a cold start misses misses that would occur even with infinite cache Capacity cache is too small to hold all data needed by the program misses that would occur even under perfect replacement policy Conflict misses that occur because of collisions due to block placement strategy misses that would not occur with full associativity February 9 2011 CS152 Spring 2011 6 Effect of Cache Parameters on Performance Larger cache size reduces capacity and conflict misses hit time will increase Higher associativity reduces conflict misses may increase hit time Larger block size reduces compulsory and capacity reload misses increases conflict misses and miss penalty February 9 2011 CS152 Spring 2011 7 Write Policy Choices Cache hit write through write both cache memory Generally higher traffic but simpler pipeline cache design write back write cache only memory is written only when the entry is evicted A dirty bit per block further reduces write back traffic Must handle 0 1 or 2 accesses to memory for each load store Cache miss no write allocate only write to main memory write allocate aka fetch on write fetch into cache Common combinations write through and no write allocate write back with write allocate February 9 2011 CS152 Spring 2011 8 Write Performance Tag Block Offset Index b t V Tag k Data 2k lines t HIT February 9 2011 WE Data Word or Byte CS152 Spring 2011 9 Reducing Write Hit Time Problem Writes take two cycles in memory stage one cycle for tag check plus one cycle for data write if hit Solutions Design data RAM that can perform read and write in one cycle restore old value after tag miss Fully associative CAM Tag caches Word line only enabled if hit Pipelined writes Hold write data for store in single buffer ahead of cache write cache data during next store s tag check February 9 2011 CS152 Spring 2011 10 Pipelining Cache Writes Address and Store Data From CPU Tag Index Store Data Delayed Write Addr Delayed Write Data Load Store S L Tags Data 1 Hit 0 Load Data to CPU Data from a store hit written into data portion of cache during tag access of subsequent store February 9 2011 CS152 Spring 2011 11 Write Buffer to Reduce Read Miss Penalty CPU RF Data Cache Unified L2 Cache Write buffer Evicted dirty lines for writeback cache OR All writes in writethrough cache Processor is not stalled on writes and read misses can go ahead of write to main memory Problem Write buffer may hold updated value of location needed by a read miss Simple scheme on a read miss wait for the write buffer to go empty Faster scheme Check write buffer addresses against read miss addresses if no match allow read miss to go ahead of writes else return value in write buffer February 9 2011 CS152 Spring 2011 12 Block level Optimizations Tags are too large i e too much overhead Simple solution Larger blocks but miss penalty could be large Sub block placement aka sector cache A valid bit added to units smaller than full block called sub blocks Only read a sub block on a miss If a tag matches is the word in the cache 100 300 204 February 9 2011 1 1 0 1 1 1 1 0 0 CS152 Spring 2011 1 0 1 13 Multilevel Caches Problem A memory cannot be large and fast Solution Increasing sizes of cache at each level CPU L1 L2 DRAM Local miss rate misses in cache accesses to cache Global miss rate misses in cache CPU memory accesses Misses per instruction misses in cache number of instructions February 9 2011 CS152 Spring 2011 14 Presence of L2 influences L1 design Use smaller L1 if there is also L2 Trade increased L1 miss rate for reduced L1 hit time and reduced L1 miss penalty Reduces average access energy Use simpler write through L1 with on chip L2 Write back L2 cache absorbs write traffic doesn t go off chip At most one L1 miss request per L1 access no dirty victim write back simplifies pipeline control Simplifies coherence issues Simplifies error recovery in L1 can use just parity bits in L1 and reload from L2 when parity error detected on L1 read February 9 2011 CS152 Spring 2011 15 Inclusion Policy Inclusive multilevel cache Inner cache holds copies of data in outer cache External coherence snoop access need only check outer cache Exclusive multilevel
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