3/17/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec13.1CS152Computer Architecture and EngineeringLecture 13Introduction to Pipelining:Datapath and ControlMarch 3rd, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.2Recap: Exceptions° Exception = unprogrammed control transfer• system takes action to handle the exception- must record the address of the offending instruction- record any other information necessary to return afterwards• returns control to user• must save & restore user state° Allows constuction of a “user virtual machine”normal control flow:sequential, jumps, branches, calls, returnsuser programSystemExceptionHandlerException:return fromexception3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.3Recap: Precise Exceptions° Precise ⇒ state of the machine is preserved as if program executed up to the offending instruction• All previous instructions completed• Offending instruction and all following instructions act as if they have not even started• Same system code will work on different implementations • Position clearly established by IBM• Difficult in the presence of pipelining, out-ot-order execution, ...• MIPS takes this position° Imprecise ⇒ system software has to figure out what is where and put it all back together° Performance goals often lead designers to forsake precise interrupts• system software developers, user, markets etc. usually wish they had not done this° Modern techniques for out-of-order execution and branch prediction help implement precise interrupts3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.4Recap: Sequential Laundry° Sequential laundry takes 6 hours for 4 loads° If they learned pipelining, how long would laundry take?ABCD3040 20 30 40 20 30 40 20 30 40 206 PM7891011MidnightTaskOrderTime3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.5Recap: Pipelining Lessons° Pipelining doesn’t help latency of single task, it helps throughput of entire workload° Pipeline rate limited by slowest pipeline stage° Multiple tasks operating simultaneously using different resources° Potential speedup = Number pipe stages° Unbalanced lengths of pipe stages reduces speedup° Time to “fill” pipeline and time to “drain” it reduces speedup° Stall for DependencesABCD6 PM789TaskOrderTime30 40 40 40 40 203/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.6Recap: Ideal PipeliningIF DCD EX MEM WBIF DCD EX MEM WBIF DCD EX MEM WBIF DCD EX MEM WBIF DCD EX MEM WBMaximum Speedup ≤ Number of stagesSpeedup ≤ Time for unpipelined operationTime for longest stageExample: 40ns data path, 5 stages, Longest stage is 10 ns, Speedup ≤ 4Assume instructionsare completely independent!3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.7° The Five Classic Components of a Computer° Today’s Topics: • Recap last lecture/finish datapath• Pipelined Control/ Do it yourself Pipelined Control• Administrivia• Hazards/Forwarding• Exceptions• Review MIPS R3000 pipelineThe Big Picture: Where are We Now? ControlDatapathMemoryProcessorInputOutput3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.8Can pipelining get us into trouble?° Yes: Pipeline Hazards• structural hazards: attempt to use the same resource two different ways at the same time- E.g., combined washer/dryer would be a structural hazard or folder busy doing something else (watching TV)• data hazards: attempt to use item before it is ready- E.g., one sock of pair in dryer and one in washer; can’t fold until get sock from washer through dryer- instruction depends on result of prior instruction still in the pipeline• control hazards: attempt to make a decision before condition isevaulated- E.g., washing football uniforms and need to get proper detergent level; need to see after dryer before next load in- branch instructions° Can always resolve hazards by waiting• pipeline control must detect the hazard• take action (or delay action) to resolve hazards3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.9ImSingle Memory is a Structural HazardInstr.OrderTime (clock cycles)LoadInstr 1Instr 2Instr 3Instr 4ALUImRegMem RegALUImRegMem RegALUImRegMem RegALURegMem RegALUImRegMem RegDetection is easy in this case! Fix: Stall Instr 3 fetch.3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.10Structural Hazards limit performance° Example: if 1.3 memory accesses per instruction and only one memory access per cycle then• average CPI ≥ 1.3• otherwise resource is more than 100% utilized3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.11° Stall: wait until decision is clear° Impact: 2 lost cycles (i.e. 3 clock cycles per branch instruction) => slow° Move decision to end of decode• save 1 cycle per branchControl Hazard Solution #1: StallInstr.OrderTime (clock cycles)AddBeqLoadALUImRegMem RegALUImRegMem RegALURegMem RegImLostpotential3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.12Reg° Predict: guess one direction then back up if wrong° Impact: 0 lost cycles per branch instruction if right, 1 if wrong (right - 50% of time)• Need to “Squash” and restart following instruction if wrong• Produce CPI on branch of (1 *.5 + 2 * .5) = 1.5• Total CPI might then be: 1.5 * .2 + 1 * .8 = 1.1 (20% branch)° More dynamic scheme: history of 1 branch (- 90%)Control Hazard Solution #2: PredictInstr.OrderTime (clock cycles)AddBeqLoadALUImRegMem RegALUIm Mem RegImALURegMem Reg3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.13Reg° Delayed Branch: Redefine branch behavior (takes place after next instruction) ° Impact: 0 clock cycles per branch instruction if can find instruction to put in “slot” (- 50% of time)° As launch more instruction per clock cycle, less usefulControl Hazard Solution #3: Delayed BranchInstr.OrderTime (clock cycles)AddBeqMiscALUImRegMem RegALUIm Mem RegImALURegMem RegLoadImALURegMem Reg3/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.14Data Hazard on r1: Read after write hazard (RAW)add r1,r2,r3sub r4,r1,r3and r6,r1,r7or r8,r1,r9xor r10,r1,r113/3/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec11.15Reg• Dependencies backwards in time are hazardsInstr.OrderTime (clock cycles)add r1,r2,r3sub r4,r1,r3and r6,r1,r7or r8,r1,r9xor r10,r1,r11IF ID/RF EX MEM WBALUImRegDmRegALUImRegDm RegALUImRegDm RegImALURegDm RegALUIm Dm RegData Hazard on r1: Read after write hazard
View Full Document
Unlocking...