Recap Exceptions System Exception Handler user program CS152 Computer Architecture and Engineering Lecture 13 Exception Introduction to Pipelining Datapath and Control return from exception normal control flow sequential jumps branches calls returns March 3rd 2004 Exception unprogrammed control transfer John Kubiatowicz www cs berkeley edu kubitron system takes action to handle the exception must record the address of the offending instruction record any other information necessary to return afterwards returns control to user must save restore user state lecture slides http inst eecs berkeley edu cs152 3 17 03 UCB Spring 2003 Allows constuction of a user virtual machine CS152 Kubiatowicz Lec13 1 3 3 04 Recap Sequential Laundry Recap Precise Exceptions Precise state of the machine is preserved as if program executed up to the offending instruction All previous instructions completed Offending instruction and all following instructions act as if they have not even started Same system code will work on different implementations Position clearly established by IBM Difficult in the presence of pipelining out ot order execution MIPS takes this position Imprecise system software has to figure out what is where and put it all back together Performance goals often lead designers to forsake precise interrupts system software developers user markets etc usually wish they had not done this Modern techniques for out of order execution and branch prediction help implement precise interrupts 3 3 04 UCB Spring 2004 CS152 Kubiatowicz Lec11 3 CS152 Kubiatowicz Lec11 2 UCB Spring 2004 6 PM 7 8 9 10 11 Midnight Time 30 40 20 30 40 20 30 40 20 30 40 20 T a s k A B O r d e r C D Sequential laundry takes 6 hours for 4 loads If they learned pipelining how long would laundry take 3 3 04 UCB Spring 2004 CS152 Kubiatowicz Lec11 4 Recap Pipelining Lessons 6 PM 7 8 9 Time 30 40 T a s k O r d e r 40 40 40 20 Recap Ideal Pipelining Multiple tasks operating simultaneously using different resources B Potential speedup Number pipe stages C Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup Stall for Dependences 3 3 04 IF Pipeline rate limited by slowest pipeline stage A D Assume instructions are completely independent Pipelining doesn t help latency of single task it helps throughput of entire workload UCB Spring 2004 CS152 Kubiatowicz Lec11 5 The Big Picture Where are We Now IF WB EX MEM WB EX MEM WB EX MEM WB EX MEM DCD DCD IF DCD WB Maximum Speedup Number of stages Speedup Time for unpipelined operation Time for longest stage Example 40ns data path 5 stages Longest stage is 10 ns Speedup 4 3 3 04 UCB Spring 2004 CS152 Kubiatowicz Lec11 6 structural hazards attempt to use the same resource two different ways at the same time E g combined washer dryer would be a structural hazard or folder busy doing something else watching TV data hazards attempt to use item before it is ready E g one sock of pair in dryer and one in washer can t fold until get sock from washer through dryer instruction depends on result of prior instruction still in the pipeline control hazards attempt to make a decision before condition is evaulated E g washing football uniforms and need to get proper detergent level need to see after dryer before next load in branch instructions Input Memory Output Today s Topics Recap last lecture finish datapath Pipelined Control Do it yourself Pipelined Control Administrivia Hazards Forwarding Exceptions Review MIPS R3000 pipeline UCB Spring 2004 MEM IF Control 3 3 04 DCD IF Processor EX Can pipelining get us into trouble Yes Pipeline Hazards The Five Classic Components of a Computer Datapath DCD Can always resolve hazards by waiting CS152 Kubiatowicz Lec11 7 pipeline control must detect the hazard take action or delay action to resolve hazards 3 3 04 UCB Spring 2004 CS152 Kubiatowicz Lec11 8 Single Memory is a Structural Hazard Structural Hazards limit performance Time clock cycles Instr 2 O r d e r Reg Reg Mem Reg Im Reg Mem Reg Im Reg Mem Reg Im Reg ALU Im average CPI 1 3 otherwise resource is more than 100 utilized Mem ALU Instr 1 Reg ALU Im ALU Load ALU I n s t r Example if 1 3 memory accesses per instruction and only one memory access per cycle then Mem Instr 3 Instr 4 Reg Detection is easy in this case Fix Stall Instr 3 fetch 3 3 04 CS152 Kubiatowicz Lec11 9 UCB Spring 2004 3 3 04 Control Hazard Solution 2 Predict Control Hazard Solution 1 Stall Reg Mem Reg Im Reg Lost potential Mem Reg Stall wait until decision is clear Impact 2 lost cycles i e 3 clock cycles per branch instruction slow Move decision to end of decode save 1 cycle per branch 3 3 04 UCB Spring 2004 CS152 Kubiatowicz Lec11 11 O r d e r Add Beq Load Im Reg Im Mem Reg Reg Mem Reg Reg ALU Reg ALU Load Im Mem ALU Beq Reg Time clock cycles ALU Add Im ALU O r d e r I n s t r Time clock cycles ALU I n s t r CS152 Kubiatowicz Lec11 10 UCB Spring 2004 Mem Im Reg Predict guess one direction then back up if wrong Impact 0 lost cycles per branch instruction if right 1 if wrong right 50 of time Need to Squash and restart following instruction if wrong Produce CPI on branch of 1 5 2 5 1 5 Total CPI might then be 1 5 2 1 8 1 1 20 branch More dynamic scheme history of 1 branch 90 3 3 04 UCB Spring 2004 CS152 Kubiatowicz Lec11 12 Control Hazard Solution 3 Delayed Branch Beq Reg Im Misc Mem Reg Reg Mem Reg Reg Mem Reg Im Reg ALU Im ALU Add ALU O r d e r Time clock cycles ALU I n s t r Data Hazard on r1 Read after write hazard RAW Mem Im Load add r1 r2 r3 sub r4 r1 r3 and r6 r1 r7 Reg or r8 r1 r9 Delayed Branch Redefine branch behavior takes place after next instruction Impact 0 clock cycles per branch instruction if can find instruction to put in slot 50 of time As launch more instruction per clock cycle less useful 3 3 04 xor r10 r1 r11 CS152 Kubiatowicz Lec11 13 UCB Spring 2004 3 3 04 Data Hazard on r1 Read after write hazard RAW Forward result from one stage to another Time clock cycles IF Time clock cycles IF Dm Im Reg Dm Im Reg Dm Im Reg xor r10 r1 r11 Reg Reg Reg Dm Reg O r d e r add r1 r2 r3 sub r4 r1 r3 and r6 r1 r7 or r8 r1 r9 ID RF EX MEM WB Reg Dm Im Reg Dm Im Reg Dm Im Reg Dm Im Reg ALU Reg I n s t r Im ALU Im Reg ALU Dm ALU Reg ALU or r8 r1 r9 WB ALU and r6 …
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