CS 152 Computer Architecture and Engineering Lecture 8 Single-Cycle (Con’t) Designing a Multicycle ProcessorRecap: A Single Cycle DatapathRecap: Flexible Instruction FetchRecap: The Single Cycle Datapath during AddRecap: The Single Cycle Datapath during LoadRecap: The Single Cycle Datapath during StoreRecap: The Single Cycle Datapath during BranchRecap: A Summary of Control SignalsStep 5: Assemble Control logicA Summary of the Control SignalsThe Concept of Local DecodingThe Encoding of ALUopThe Decoding of the “func” FieldThe Truth Table for ALUctrStep 5: Logic for each control signalThe “Truth Table” for the Main ControlThe “Truth Table” for RegWritePLA Implementation of the Main ControlAdministrative IssuesThe Big Picture: Where are We Now?Abstract View of our single cycle processorWhat’s wrong with our CPI=1 processor?Memory Access TimeReducing Cycle TimeWorst Case Timing (Load)Basic Limits on Cycle TimePartitioning the CPI=1 DatapathExample Multicycle DatapathRecall: Step-by-step Processor DesignStep 4: R-rtype (add, sub, . . .)Step 4: Logical immedStep 4 : LoadStep 4 : StoreStep 4 : BranchAlternative datapath (book): Multiple Cycle DatapathOur Control ModelStep 4 Control Specification for multicycle procTraditional FSM ControllerStep 5 (datapath + state diagram control)Mapping RTs to Control PointsAssigning States(Mostly) Detailed Control Specification (missing0)Performance EvaluationController DesignExample: Jump-CounterUsing a Jump CounterOur MicrosequencerMicroprogram Control SpecificationOverview of ControlSummarySummary (cont’d)CS 152Computer Architecture and EngineeringLecture 8Single-Cycle (Con’t)Designing a Multicycle ProcessorFebruary 23, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.2Recap: A Single Cycle Datapath°Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit°We have everything except control signals (underline)32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemory32MemWrALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.3Recap: Flexible Instruction Fetch°Branch (nPC_sel = “Br”):•if (Equal == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4°Other (nPC_sel = “+4”): •PC=PC+4°What is encoding of nPC_sel?•Direct MUX select?•Branch / not branch°Let’s choose second optionnPC_sel Equal MUX0 x 01 0 01 1 1AdrInstMemoryAdderAdderPCClk00Mux4nPC_selimm16Instruction<31:0>01EqualnPC_MUX_sel2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.4Recap: The Single Cycle Datapath during Add32ALUctr = AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 1ExtenderMuxMux3216imm16ALUSrc = 0ExtOp = xMuxMemtoReg = 0ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>°R[rd] <- R[rs] + R[rt]010101<21:25><16:20><11:15><0:15>Imm16RdRsRtop rs rt rd shamt funct061116212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.6Recap: The Single Cycle Datapath during Load32ALUctr = AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 0ExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = 1ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt°R[rt] <- Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate016212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.7Recap: The Single Cycle Datapath during Store32ALUctr = AddClkbusWRegWr = 03232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = xExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = xClkData InWrEn32AdrDataMemory32MemWr = 1ALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt°Data Memory {R[rs] + SignExt[imm16]} <- R[rt]op rs rt immediate016212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.8Recap: The Single Cycle Datapath during Branch32ALUctr =SubClkbusWRegWr = 03232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = xExtenderMuxMux3216imm16ALUSrc = 0ExtOp = xMuxMemtoReg = xClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt°if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0op rs rt immediate016212631nPC_sel= “Br”2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.9Recap: A Summary of Control Signalsinst Register TransferADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4nPC_sel = “Br”, ALUctr = “sub”2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.10Step 5: Assemble Control logicALUctrRegDstALUSrcExtOpMemtoRegMemWrEqualInstruction<31:0><21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_selAdrInstMemoryDATA PATHDecoderOp<21:25>FunRegWr2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.11A Summary of the Control Signalsadd sub ori lw sw beqRegDstALUSrcMemtoRegRegWriteMemWritenPCselExtOpALUctr<2:0>100100xAdd100100xSubtract0101000Or0111001Addx1x0101Addx0x001xSubtractop target addressop rs rt rd shamt funct061116212631op rs rtimmediateR-typeI-typeJ-typeadd, subori, lw, sw, beqjumpfuncop 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100Appendix A10 0000See 10 0010We Don’t Care :-)2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.12The Concept of Local DecodingMainControlop6ALUControl(Local)funcN6ALUopALUctr3ALUR-type ori lw sw beqRegDstALUSrcMemtoRegRegWriteMemWriteBranchExtOpALUop<N:0>100100x“R-type”0101000Or0111001Addx1x0101Addx0x001xSubtractop 00
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