CS 152 Computer Architecture and Engineering Lecture 8 Single Cycle Con t Designing a Multicycle Processor February 23 2004 John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 Recap A Single Cycle Datapath Rs Rt Rd and Imed16 hardwired into datapath from Fetch Unit We have everything except control signals underline Instruction 31 0 1 Mux 0 RegWr 5 5 Rs 5 Rt Rt Equal ALUctr ExtOp UCB Spring 2004 MemtoReg 0 32 Data In 32 ALUSrc 2 23 04 Imm16 Clk WrEn Adr 32 Mux 0 1 32 ALU 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32 bit Registers busB 32 Rd MemWr busA busW Rs 0 15 Clk 11 15 RegDst Rt 21 25 Rd Instruction Fetch Unit 16 20 nPC sel 1 Data Memory CS152 Kubiatowicz Recap Flexible Instruction Fetch Branch nPC sel Br if Equal 1 then PC PC 4 SignExt imm16 4 else PC PC 4 Other nPC sel 4 PC PC 4 Inst Memory nPC sel Adr Equal What is encoding of nPC sel nPC MUX sel 4 00 0 PC Mux Adder imm16 Direct MUX select Branch not branch Let s choose second option Adder 2 23 04 Instruction 31 0 1 nPC sel 0 1 1 Equal x 0 1 MUX 0 0 1 Clk UCB Spring 2004 CS152 Kubiatowicz Recap The Single Cycle Datapath during 26 21 16 11 6 Add 31 op rs rt rd shamt R rd R rs R rt 5 32 ExtOp x UCB Spring 2004 Clk Imm16 MemtoReg 0 0 32 Data In 32 ALUSrc 0 2 23 04 Rd Equal MemWr 0 ALU 16 Extender imm16 1 Rs WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Rt 0 15 5 ALUctr Add Rt 11 15 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr 1 busW Rt Instruction Fetch Unit 16 20 RegDst 1 Rd funct Instruction 31 0 21 25 nPC sel 4 0 1 Data Memory CS152 Kubiatowicz Recap The Single Cycle Datapath during 26 21 16 Load 31 op rs rt 0 immediate R rt Data Memory R rs SignExt imm16 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Rt ExtOp 1 UCB Spring 2004 0 32 Data In 32 ALUSrc 1 2 23 04 Imm16 MemtoReg 1 Clk Mux 32 Rd Equal MemWr 0 ALU 16 Extender imm16 1 Rs 0 15 5 ALUctr Add Rt 11 15 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr 1 5 busW Rt 16 20 RegDst 0 Rd Instruction Fetch Unit 21 25 nPC sel 4 Instruction 31 0 1 WrEn Adr Data Memory 32 CS152 Kubiatowicz Recap The Single Cycle Datapath during 26 21 16 Store 31 op rs rt 0 immediate Data Memory R rs SignExt imm16 R rt 5 Equal ALU 16 Extender imm16 1 2 23 04 ExtOp 1 32 UCB Spring 2004 Rd Clk Imm16 MemtoReg x MemWr 1 0 32 Data In 32 ALUSrc 1 Rs WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Rt 0 15 5 ALUctr Add Rt 11 15 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr 0 busW Rt 16 20 RegDst x Rd Instruction Fetch Unit 21 25 nPC sel 4 Instruction 31 0 1 Data Memory CS152 Kubiatowicz Recap The Single Cycle Datapath during 26 21 16 Branch 31 op rs rt 0 immediate if R rs R rt 0 then Zero 1 else Zero 0 Instruction 31 0 5 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 32 Imm16 MemtoReg x UCB Spring 2004 0 32 Data In 32 ALUSrc 0 ExtOp x Rd Clk WrEn Adr 32 Mux 1 Rs Equal MemWr 0 ALU 16 Extender imm16 2 23 04 Rt ALUctr Sub 0 15 5 Rt 11 15 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr 0 busW Rt 21 25 RegDst x Rd Instruction Fetch Unit 16 20 nPC sel Br 1 Data Memory CS152 Kubiatowicz Recap A Summary of Control Signals inst Register Transfer ADD R rd R rs R rt PC PC 4 ALUsrc RegB ALUctr add RegDst rd RegWr nPC sel 4 SUB R rd R rs R rt PC PC 4 ALUsrc RegB ALUctr sub RegDst rd RegWr nPC sel 4 ORi R rt R rs zero ext Imm16 PC PC 4 ALUsrc Im Extop Z ALUctr or RegDst rt RegWr nPC sel 4 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 ALUsrc Im Extop Sn ALUctr add MemtoReg RegDst rt RegWr nPC sel 4 STORE MEM R rs sign ext Imm16 R rs PC PC 4 ALUsrc Im Extop Sn ALUctr add MemWr nPC sel 4 BEQ if R rs R rt then PC PC sign ext Imm16 00 else PC PC 4 nPC sel Br ALUctr sub 2 23 04 UCB Spring 2004 CS152 Kubiatowicz Step 5 Assemble Control logic Instruction 31 0 Rd 0 15 Rs 11 15 Rt 16 20 Op Fun 21 25 Adr 21 25 Inst Memory Imm16 Decoder nPC sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Equal DATA PATH 2 23 04 UCB Spring 2004 CS152 Kubiatowicz A Summary of the Control Signals See Appendix A func 10 0000 10 0010 We Don t Care op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 add 1 0 sub 1 0 ori 0 1 lw 0 1 sw x 1 beq x 0 MemtoReg RegWrite MemWrite 0 1 0 0 1 0 0 1 0 1 1 0 x 0 1 x 0 0 nPCsel 0 0 0 0 0 1 x Add x Subtract 0 Or 1 Add 1 Add x RegDst ALUSrc ExtOp ALUctr 2 0 31 26 21 16 R type op rs rt I type op rs rt J type op 2 23 04 11 rd 6 shamt immediate target address UCB Spring 2004 Subtract 0 funct add sub ori lw sw beq jump CS152 Kubiatowicz The Concept of Local Decoding op 00 0000 R type 00 1101 10 0011 10 1011 00 0100 ori lw sw beq RegDst ALUSrc MemtoReg 1 0 0 0 1 0 0 1 1 x 1 x x 0 x RegWrite MemWrite Branch 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 x R type 0 Or 1 Add 1 Add x ExtOp ALUop N 0 op 6 Main Control func 6 ALUop 2 23 04 UCB Spring 2004 ALUctr 3 ALU N ALU Control Local Subtract CS152 Kubiatowicz The Encoding of ALUop op 6 Main Control func 6 ALUop N ALU Control Local ALUctr 3 ALUop has to be 2 bits wide to represent 1 R type instructions I type instructions that require the ALU to perform 2 Or 3 Add and 4 Subtract ALUop Symbolic ALUop 2 0 2 23 04 R type R type 1 00 ori Or 0 10 UCB Spring 2004 lw Add 0 00 sw Add 0 00 beq Subtract 0 01 CS152 Kubiatowicz The …
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