CS 152 Computer Architecture and Engineering Lecture 3 Single Cycle Wrap Up 2005 1 25 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB Last Time Goal 1 an R format CPU Syntax ADD 8 9 10 opcode Sample ADD 8 SUB 4 AND 9 rs program 9 10 8 3 8 4 How registers get their initial values are not of concern to us right now CS 152 L3 Single Cycle Wrap up rt Semantics 8 9 10 rd shamt funct No branches or jumps machine only runs straight line code No loads or stores machine has no use for data memory only instruction memory UC Regents Spring 2005 UCB Last Time An R format CPU design Decode fields to get ADD 8 9 10 opcode rs rt rd shamt funct Logic op 5 5 5 32 RegFile rs1 rd1 rs2 32 ws 32 wd 32 CS 152 L3 Single Cycle Wrap up rd2 32 A L U 32 WE UC Regents Spring 2005 UCB Today s Lecture Single Cycle Wrap up Design stand alone machines for other major classes of instructions immediate ALU branches load store Learn how to efficiently merge single function machines to make one general purpose machine Implementing control structures for the single cycle datapath CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB op rs rt rd shamt funct Goal 2 add I format ALU instructions 6 bits 5 bits 5 bits Syntax ORI 8 9 64 31 26 op 6 bits 31 26 ord op In 6 bits 21 5 bits 5 bits 6 bits Semantics 8 9 64 16 rs rt 5 bits 5 bits 21 16 this example rs rt 5 bits 5 bits 0 immediate 16 bits 9 is rs and 8 is rt 0 immediate 16 bits 16 bit immediate extended to 32 bits 31 26 21 16 Zero extend 0x8000 0x00008000 0 op rs rt immediate 0x8000 0xFFFF8000 6 bitsSign extend 5 bits 5 bits 16 bits Some MIPS instructions zero extend immediate field other instructions sign extend CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB op rs rt rd shamt 6 bits 5 bits 5 bits of the 5 bitsI format 5 bits Computing engine 31 Decode fields to get 26 21 16 ORI 8 9 64 op 6 bits 31 26 Word op 6 bits 5 31 funct 6 bits CPU 526 5 op 6 bits32 rs 5 bits 21 rs 5 bits RegFile rs1 rs2 21 rd1 ws rs rt 5 bits 16 rt 5 bits immediate 16 bits 0 Logic immediate op 32 16 bits 32 16 rt 32 rd2 wd 5 bits WE 5 bits 0 Ext 32 immediate 16 bits A L U 32 0 In a Verilog implementation what should we do with rs2 CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB Merging data paths opcode rs rt rd shamt funct Logic R format Add muxes op Step 1a The MIPS lite Subset for 32 today 5 32 M 32 ADD and SUB 31 op 6 bits 32 U addU X rd rs rt subU rd rs rt 5 526 32 ws 32 21 rs wd 5 bits rd2rt WE 16 5 bits 26 21 16 op ori rt rs imm16 6 bits 31 26 LOAD and STORE Word op lw rt rs imm16 6 bits rs 5 bits 21 rs 5 bits rt 5 bits 16 rt 5 bits 32 OR Immediate 31 RegFile rs1 rd1 rs2 How many sw rt rs Where imm16 BRANCH beq rs rt imm16 CS 152 L3 Single Cycle Wrap up 5 31 526 5 op 6 bits32 11 rd 5 bits ws rs wd 5 bits rd2 WE 32shamt 5 bits 6 bits immediate 16 bits 0 Logic immediate op 32 16 bits 32 16 rt 32 5 bits 32 A 0 L U funct 0 I format RegFile rs1 rs2 21 rd1 6 Ext 32 immediate 16 bits A L U 32 0 UC Regents Spring 2005 UCB The merged data path opcode rs rt rd shamt funct ALUctr op The MIPS lite Subset for today 5 31 5 5 26 op RegDest 6 bits 32 RegFile rs1 rd1 rs2 ws wd 21 rs 5 bits rd2 WE 32 32 32 16 rt 5 bits Ext ExtOp 31 26 op 6 bits 21 rs 5 bits CS 152 L3 Single Cycle Wrap up A L 6U 1132 rd 5 bits shamt 5 bits 0 funct 6 bits ALUsrc 16 rt 5 bits 32 0 immediate 16 bits UC Regents Spring 2005 UCB Administrivia Upcoming deadlines Thursday Lab 2 preliminary design document due to TAs via email 11 59 PM Friday Design Document Review 12 1 119 Cory For 61 c students 150 Lab Lecture 1 1 2 PM 125 Cory Monday Lab 2 final design document due to TAs via email 11 59 PM CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB Memory Instructions CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Loads Stores and Data Memory 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Syntax LW 1 30 2 31 26 21 16 Syntax SW 3 10 4 0 ord op immediate Action 1 rsM 2 rt30 Action M 4 10 3 6 bits 5 bits 5 bits 16 bits Zero extend or sign extend immediate field 31 32 Data 26Memory opAddr 6 bits 21 rs 32 Dout 5 bits Reads are combinational 16 0 address on Addr rt Put a stableimmediate a short time later Dout is ready 5 bits 16 bits Din 32 WE Writes are clocked If WE is high memory Addr captures Din on positive edge of clock Note Not a realistic main memory DRAM model CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB Adding data memory to the data path 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 ALUctr op 32 The MIPS lite Subset for today wd RegDest 31 32 32 26 32 Addr 21 RegWr rs 5 bits 26 21 32 Dout WE Din Ext op 6 bits 31 rd2 Data Memory A L U 32 16 ALUsrc 11 rt rd 5 bits 5 bits 6 ExtOp 16 WE shamt 5 bits 0 MemToReg MemWr funct 6 bits 0 op rs rt immediate 6 bitsLW 1 5 bits30 2 5 bits Syntax Syntax 16 SWbits 3 10 4 31 26 21 16 0 Word Action 1 M 2 30 Action M 4 10 3 op rs rt immediate CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB Branch Instructions CS 152 L3 Single Cycle Wrap up UC Regents Spring 2005 UCB 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Conditional Branches in MIPS 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits …
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