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Berkeley COMPSCI 152 - Lecture 4 – Timing

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Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 25CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCB2004-09-07 Dave Patterson(www.cs.berkeley.edu/~patterson)John Lazzaro (www.cs.berkeley.edu/~lazzaro)www-inst.eecs.berkeley.edu/~cs152/CS152 – Computer Architecture andEngineeringLecture 4 – TimingCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBLast Time: Test plan for your projectcomplete processor testingTop-downtestingBottom-uptestingunit testingprocessortestingwithself-checksWhich testing types are good for each epoch?processorassemblycompletecorrectlyexecutes singleinstructionscorrectlyexecutes shortprogramsTimeEpoch 1 Epoch 2Epoch 3 Epoch 4unit testingearlymultiunit testinglatermulti-unit testingprocessortestingwithself-checksmulti-unit testingunit testingdiagnosticscomplete processor testingverificationprocessortestingwithself-checksdiagnosticsprocessortestingwithself-checksmulti-unit testingunit testingdiagnosticsCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBOutline - TimingTeam networking break!A clocked logic circuit primerMore clocked logic circuitsCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBArchitects draw blocks ...Circuit designers draw ??? Logic is where they meet.CS 152 L02 Design as a Team Sport () UC Regents Fall 2004 © UCBArchitects reach logic top-down ...Next State Combinational Logicnext_Gnext_R next_YR G YChangeRstwire next_R, next_Y, next_G;assign next_R = rst ? 1’b1 : (change ? Y : R); assign next_Y = rst ? 1’b0 : (change ? G : Y);assign next_G = rst ? 1’b0 : (change ? R : G); Is this structural Verilog?CS 152 L02 Design as a Team Sport () UC Regents Fall 2004 © UCBEEs reach logic bottom-up ...Can you build a processorentirely out of NAND gates?Small number of high-performance logic circuits. For some definition of performance.CS 152 L02 Design as a Team Sport () UC Regents Fall 2004 © UCBLogic Synthesis bridges the gapassign next_R = rst ? 1’b1 : (change ? Y : R); assign next_Y = rst ? 1’b0 : (change ? G : Y);assign next_G = rst ? 1’b0 : (change ? R : G); It’s easier to work at one level of abstraction if you have a basic understanding of the level below.CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBAdministrivia - Team Networking Break!First homework due 9/15.Lab 1 due Monday 9/13.Mini-Lab 2 this Friday (9/10).Remember to do the pre-lab!Lab 2 goes out on 9/14. The first team lab (next break)UC Regents Fall 2004 © UCBCS 152 L03 Testing Processors ()A Logic Circuit PrimerCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBInverters: A simple transistor model“1”“0”pFET.A switch. “On” if gate is grounded.nFET.A switch. “On” if gate is at Vdd.“1”“0”“1”“0”CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBTransistors as water valvesIf electrons are water molecules,and a capacitor a bucket ...A “on” p-FET fillsup the capacitor with charge. A “on” n-FET empties the bucket.“1”“0”TimeWater level“0”“1”TimeWater levelCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBWhat is the bucket? A gate’s “fan-out”.Driving other gates slows a gate down.Driving wires slows a gate down.“Fan-out”: The number of gate inputs driven by a gate’s output.CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBA closer look at fan-out ...Driving more gates adds delay.Linear model works for reasonablefan-outCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBPropagation delay graphs ...1->0CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBIntuition: Critical paths ...x = g(a, b, c, d, e, f)If d going 0-to-1 switches x 0-to-1, delay is T1.If a going 0-to-1 switches x 0-to-1, delay is T2.Would you be surprised if T1 > T2? Why?T1T2T2 might be the critical (worst-case delay) path.CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBWhy “might”? Wires have delay too ...Looksbenign,but ...CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBTeam Networking Break!Optimal team size? Min/max?Disagreements are inevitable.Build a bridge and get over it.Lab 2 goes out on 9/14. Time to form your team.Talk out little problems before they get big. Communicate.UC Regents Fall 2004 © UCBCS 152 L03 Testing Processors ()Clocked Logic CircuitsCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBFrom Delay Models to Timing Analysisf T1 MHz 1 μs10 MHz 100 ns100 MHz 10 ns1 GHz 1 nsTiming AnalysisWhat is the smallest T that produces correct operation?CS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBTiming Analysis and Logic DelayCan T be smaller than worst-casedelay through CL? Register:An Array of Flip-FlopsCombinational LogicCS 152 L02 Design as a Team Sport () UC Regents Fall 2004 © UCBFlip Flops have internal delays ...D QCLKValue of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.DQt_setupt_clk-to-QCS 152 L03 Testing Processors () UC Regents Fall 2004 © UCBConclusion -- TimingFlip-flops: setup and clk-to-QCritical path limits clock speedLogic delay: fan-out and


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Berkeley COMPSCI 152 - Lecture 4 – Timing

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