CS152 Computer Architecture and Engineering Lecture 4 Timing 2004 09 07 Dave Patterson www cs berkeley edu patterson John Lazzaro www cs berkeley edu lazzaro www inst eecs berkeley edu cs152 CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Last Time Test plan for your project Top down testing complete processor testing processor testing with self checks multi unit testing Which testing types are good for each epoch Epoch 1 Epoch 2 Epoch 3 Epoch 4 unit testing early processor processor complete testing testing processor with with testing self checks self checks verificati on processor multi multi unit multi unit unit testing testing testing testing with unit testing unit testing self checks later unit testing Bottom up testing CS 152 L03 Testing Processors diagnostidiagnosti diagnosti cs cs cs Time processor assembly complete correctly executes single instructions correctly executes short programs UC Regents Fall 2004 UCB Outline Timing A clocked logic circuit primer Team networking break More clocked logic circuits CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Architects draw blocks Circuit designers draw CS 152 L03 Testing Processors Logic is where they meet UC Regents Fall 2004 UCB Architects reach logic top down Rst Change Next State Combinational Logic R G Y next R next G next Y wire next R next Y next G assign next R rst 1 b1 change Y R assign next Y rst 1 b0 change G Y assign next G rst 1 b0 change R G Is this structural Verilog CS 152 L02 Design as a Team Sport UC Regents Fall 2004 UCB EEs reach logic bottom up Small number of high performance logic circuits For some definition of performance Can you build a processor entirely out of NAND gates CS 152 L02 Design as a Team Sport UC Regents Fall 2004 UCB Logic Synthesis bridges the gap assign next R rst 1 b1 change Y R assign next Y rst 1 b0 change G Y It s easier to work at assign next G rst 1 b0 change R one level of G abstraction if you have a basic understanding of the level below CS 152 L02 Design as a Team Sport UC Regents Fall 2004 UCB Administrivia Team Networking Break Mini Lab 2 this Friday 9 10 Remember to do the pre lab Lab 1 due Monday 9 13 First homework due 9 15 Lab 2 goes out on 9 14 The first team lab next break CS 152 L03 Testing Processors UC Regents Fall 2004 UCB A Logic Circuit Primer CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Inverters A simple transistor model 1 0 1 0 1 0 CS 152 L03 Testing Processors pFET A switch On if gate is grounded nFET A switch On if gate is at Vdd UC Regents Fall 2004 UCB Transistors as water valves If electrons are water molecules and a capacitor a bucket 1 A on p FET fills up the capacitor with charge 0 1 Water level Time A on n FET empties the bucket 0 Water level CS 152 L03 Testing Processors Time UC Regents Fall 2004 UCB What is the bucket A gate s fan out Fan out The number of gate inputs driven by a gate s output Driving other gates slows a gate down Driving wires slows a gate down CS 152 L03 Testing Processors UC Regents Fall 2004 UCB A closer look at fan out Driving more gates adds delay Linear model works for reasonable fan out CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Propagation delay graphs 1 0 CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Intuition Critical paths T2 might be the critical worstcase delay path T1 T2 x g a b c d e f If d going 0 to 1 switches x 0 to 1 delay is T1 If a going 0 to 1 switches x 0 to 1 delay is T2 Would you be surprised if T1 T2 Why CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Why might Wires have delay too Looks benign but CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Team Networking Break Lab 2 goes out on 9 14 Time to form your team Optimal team size Min max Talk out little problems before they get big Communicate Disagreements are inevitable Build a bridge and get over it CS 152 L03 Testing Processors UC Regents Fall 2004 UCB Clocked Logic Circuits CS 152 L03 Testing Processors UC Regents Fall 2004 UCB From Delay Models to Timing Analysis Timing Analysis What is the smallest T that produces correct operation CS 152 L03 Testing Processors f T 1 MHz 1 s 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns UC Regents Fall 2004 UCB Timing Analysis and Logic Delay Register An Array of Flip Flops Combinational Logic CS 152 L03 Testing Processors Can T be smaller than worst case UC Regents Fall 2004 UCB Flip Flops have internal delays D Q Value of D is sampled on positive clock edge sampled value for rest Q outputs of cycle t setup CLK D Q CS 152 L02 Design as a Team Sport t clk to Q UC Regents Fall 2004 UCB Conclusion Timing Logic delay fan out and wires Flip flops setup and clk to Q Critical path limits clock speed CS 152 L03 Testing Processors UC Regents Fall 2004 UCB
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