CS 152 Computer Architecture and Engineering Lecture 15 VLIW Machines and Statically Scheduled ILP Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 March 16 2010 CS152 Spring 2010 Last time in Lecture 14 BTB allows prediction very early in pipeline Also handles jump register although return address stack handles subroutine returns better Unified physical register file machines remove data values from ROB All values only read and written during execution Only register tags held in ROB Allocate resources ROB slot destination physical register memory reorder queue location during decode Issue window can be separated from ROB and made smaller than ROB allocate in decode free after instruction completes Free resources on commit Speculative store buffer holds store values before commit to allow load store forwarding Can execute later loads past earlier stores when addresses known or predicted no dependence March 16 2010 CS152 Spring 2010 2 Datapath Branch Prediction and Speculative Execution Update predictors Branch Prediction kill kill Branch Resolution kill PC Fetch Decode Rename kill Reorder Buffer Commit Reg File March 16 2010 Branch ALU MEM Unit Execute CS152 Spring 2010 Store Buffer D 3 Speculative Store Buffer Speculative Store Buffer V V V V V V S S S S S S Load Address Tag Tag Tag Tag Tag Tag Data Data Data Data Data Data L1 Data Cache Tags Data Store Commit Path Load Data On store execute mark entry valid and speculative and save data and tag of instruction On store commit clear speculative bit and eventually move data to cache On store abort clear valid bit March 16 2010 CS152 Spring 2010 4 Speculative Store Buffer Speculative Store Buffer V V V V V V S S S S S S Tag Tag Tag Tag Tag Tag Load Address Data Data Data Data Data Data L1 Data Cache Tags Store Commit Path Data Load Data If data in both store buffer and cache which should we use Speculative store buffer If same address in store buffer twice which should we use Youngest store older than load March 16 2010 CS152 Spring 2010 5 Instruction Flow in Unified Physical Register File Pipeline Fetch Get instruction bits from current guess at PC place in fetch buffer Update PC using sequential address or branch predictor BTB Decode Rename Take instruction from fetch buffer Allocate resources to execute instruction Destination physical register if instruction writes a register Entry in reorder buffer to provide in order commit Entry in issue window to wait for execution Entry in memory buffer if load or store Decode will stall if resources not available Rename source and destination registers Check source registers for readiness Insert instruction into issue window reorder buffer memory buffer March 16 2010 CS152 Spring 2010 6 Memory Instructions Split store instruction into two pieces during decode Address calculation store address Data movement store data Allocate space in program order in memory buffers during decode Store instructions Store address calculates address and places in store buffer Store data copies store value into store buffer Store address and store data execute independently out of issue window Stores only commit to data cache at commit point Load instructions Load address calculation executes from window Load with completed effective address searches memory buffer Load instruction may have to wait in memory buffer for earlier store ops to resolve March 16 2010 CS152 Spring 2010 7 Issue Stage Writebacks from completion phase wakeup some instructions by causing their source operands to become ready in issue window In more speculative machines might wake up waiting loads in memory buffer Need to select some instructions for issue Arbiter picks a subset of ready instructions for execution Example policies random lower first oldest first critical first Instructions read out from issue window and sent to execution March 16 2010 CS152 Spring 2010 8 Execute Stage Read operands from physical register file and or bypass network from other functional units Execute on functional unit Write result value to physical register file or store buffer if store Produce exception status write to reorder buffer Free slot in instruction window March 16 2010 CS152 Spring 2010 9 Commit Stage Read completed instructions in order from reorder buffer may need to wait for next oldest instruction to complete If exception raised flush pipeline jump to exception handler Otherwise release resources Free physical register used by last writer to same architectural register Free reorder buffer slot Free memory reorder buffer slot March 16 2010 CS152 Spring 2010 10 Superscalar Control Logic Scaling Issue Width W Issue Group Previously Issued Instructions Lifetime L Each issued instruction must somehow check against W L instructions i e growth in hardware W W L For in order machines L is related to pipeline latencies and check is done during issue interlocks or scoreboard For out of order machines L also includes time spent in instruction buffers instruction window or ROB and check is done by broadcasting tags to waiting instructions at write back completion As W increases larger instruction window is needed to find enough parallelism to keep machine busy greater L Out of order control logic grows faster than W2 W3 March 16 2010 CS152 Spring 2010 11 Out of Order Control Complexity MIPS R10000 Control Logic SGI MIPS Technologies Inc 1995 March 16 2010 CS152 Spring 2010 12 Sequential ISA Bottleneck Sequential source code Superscalar compiler Sequential machine code a foo b for i 0 i Find independent operations Schedule operations Superscalar processor Check instruction dependencies March 16 2010 Schedule execution CS152 Spring 2010 13 VLIW Very Long Instruction Word Int Op 1 Int Op 2 Mem Op 1 Mem Op 2 FP Op 1 FP Op 2 Two Integer Units Single Cycle Latency Two Load Store Units Three Cycle Latency Two Floating Point Units Four Cycle Latency Multiple operations packed into one instruction Each operation slot is for a fixed function Constant operation latencies are specified Architecture requires guarantee of Parallelism within an instruction no cross operation RAW check No data use before data ready no data interlocks March 16 2010 CS152 Spring 2010 14 VLIW Compiler Responsibilities Schedules to maximize parallel execution Guarantees intra instruction parallelism Schedules to avoid data hazards no interlocks Typically separates
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