Slide 1Last time in Lecture 14Slide 3Speculative Store BufferSpeculative Store BufferInstruction Flow in Unified Physical Register File PipelineMemory InstructionsIssue StageExecute StageCommit StageSuperscalar Control Logic ScalingOut-of-Order Control Complexity: MIPS R10000Sequential ISA BottleneckVLIW: Very Long Instruction WordVLIW Compiler ResponsibilitiesEarly VLIW MachinesLoop ExecutionLoop UnrollingScheduling Loop Unrolled CodeSoftware PipeliningSoftware Pipelining vs. Loop UnrollingCS152 AdministriviaWhat if there are no loops?Trace Scheduling [ Fisher,Ellis]Problems with “Classic” VLIWVLIW Instruction EncodingRotating Register FilesRotating Register FileRotating Register File (Previous Loop Example)Cydra-5: Memory Latency Register (MLR)AcknowledgementsMarch 16, 2010 CS152, Spring 2010CS 152 Computer Architecture and Engineering Lecture 15 - VLIW Machines and Statically Scheduled ILPKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs152March 16, 2010 CS152, Spring 20102Last time in Lecture 14•BTB allows prediction very early in pipeline–Also handles jump register, although return address stack handles subroutine returns better•Unified physical register file machines remove data values from ROB–All values only read and written during execution–Only register tags held in ROB–Allocate resources (ROB slot, destination physical register, memory reorder queue location) during decode–Issue window can be separated from ROB and made smaller than ROB (allocate in decode, free after instruction completes)–Free resources on commit•Speculative store buffer holds store values before commit to allow load-store forwarding•Can execute later loads past earlier stores when addresses known, or predicted no dependenceMarch 16, 2010 CS152, Spring 20103FetchDecode & RenameReorder BufferPCBranchPredictionUpdate predictorsCommitDatapath: Branch Predictionand Speculative ExecutionBranchResolutionBranchUnitALUReg. FileMEMStore BufferD$ExecutekillkillkillkillMarch 16, 2010 CS152, Spring 20104Speculative Store Buffer•On store execute:–mark entry valid and speculative, and save data and tag of instruction.•On store commit: –clear speculative bit and eventually move data to cache•On store abort:– clear valid bitDataLoad AddressTagsStore Commit PathSpeculative Store BufferL1 Data CacheLoad DataTag DataSVTag DataSVTag DataSVTag DataSVTag DataSVTag DataSVMarch 16, 2010 CS152, Spring 20105Speculative Store Buffer•If data in both store buffer and cache, which should we use?Speculative store buffer•If same address in store buffer twice, which should we use?Youngest store older than loadDataLoad AddressTagsStore Commit PathSpeculative Store BufferL1 Data CacheLoad DataTag DataSVTag DataSVTag DataSVTag DataSVTag DataSVTag DataSVMarch 16, 2010 CS152, Spring 20106Instruction Flow in Unified Physical Register File Pipeline•Fetch–Get instruction bits from current guess at PC, place in fetch buffer–Update PC using sequential address or branch predictor (BTB)•Decode/Rename–Take instruction from fetch buffer–Allocate resources to execute instruction:»Destination physical register, if instruction writes a register»Entry in reorder buffer to provide in-order commit»Entry in issue window to wait for execution»Entry in memory buffer, if load or store–Decode will stall if resources not available–Rename source and destination registers–Check source registers for readiness–Insert instruction into issue window+reorder buffer+memory bufferMarch 16, 2010 CS152, Spring 20107Memory Instructions•Split store instruction into two pieces during decode:–Address calculation, store-address–Data movement, store-data•Allocate space in program order in memory buffers during decode•Store instructions:–Store-address calculates address and places in store buffer–Store-data copies store value into store buffer–Store-address and store-data execute independently out of issue window–Stores only commit to data cache at commit point•Load instructions:–Load address calculation executes from window–Load with completed effective address searches memory buffer–Load instruction may have to wait in memory buffer for earlier store ops to resolveMarch 16, 2010 CS152, Spring 20108Issue Stage•Writebacks from completion phase “wakeup” some instructions by causing their source operands to become ready in issue window–In more speculative machines, might wake up waiting loads in memory buffer•Need to “select” some instructions for issue–Arbiter picks a subset of ready instructions for execution–Example policies: random, lower-first, oldest-first, critical-first•Instructions read out from issue window and sent to executionMarch 16, 2010 CS152, Spring 20109Execute Stage•Read operands from physical register file and/or bypass network from other functional units•Execute on functional unit•Write result value to physical register file (or store buffer if store)•Produce exception status, write to reorder buffer•Free slot in instruction windowMarch 16, 2010 CS152, Spring 201010Commit Stage•Read completed instructions in-order from reorder buffer–(may need to wait for next oldest instruction to complete)•If exception raised–flush pipeline, jump to exception handler•Otherwise, release resources:–Free physical register used by last writer to same architectural register–Free reorder buffer slot–Free memory reorder buffer slotMarch 16, 2010 CS152, Spring 201011Superscalar Control Logic Scaling•Each issued instruction must somehow check against W*L instructions, i.e., growth in hardware W*(W*L)•For in-order machines, L is related to pipeline latencies and check is done during issue (interlocks or scoreboard)•For out-of-order machines, L also includes time spent in instruction buffers (instruction window or ROB), and check is done by broadcasting tags to waiting instructions at write back (completion)•As W increases, larger instruction window is needed to find enough parallelism to keep machine busy => greater L=> Out-of-order control logic grows faster than W2 (~W3)Lifetime LIssue GroupPreviously Issued InstructionsIssue Width WMarch 16, 2010 CS152, Spring 201012Out-of-Order Control Complexity:MIPS R10000Control Logic[ SGI/MIPS Technologies Inc., 1995 ]March 16, 2010 CS152, Spring 201013Check instruction
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