CS 152 L12: Memory and Interfaces UC Regents Fall 2006 © UCB2006-10-10John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 12 – Memory and Interfaceswww-inst.eecs.berkeley.edu/~cs152/TAs: Udam Saini and Jue SunCS 152 L12: Memory and Interfaces UC Regents Fall 2006 © UCBState is coded as the amount of energy stored by a device.+++ +++--- ---Last Time: Storing a Bit as Q = CVState is read by sensing the amount of energy+++ +++--- ---1.5V Problems: noise changes Q (up or down), parasitics leak or source Q. Fortunately, Q cannot change instantaneously, but that only gets us in the ballpark.UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesLast Time: Storing Bits ReliablyStore more energy than we expect from the noise.Q = CV. To store more charge, use a bigger V or make a bigger C.Cost: Power, chip size.Example: 1 bit per capacitor.Write 1.5 volts on C.To read C, measure V.V > 0.75 volts is a “1”.V < 0.75 volts is a “0”.Cost: Could have stored many bits on that capacitor.Represent stateas charge in ways that are robust to noise.Correct small state errors that are introduced by noise.Ex: read C every 1 msIs V > 0.75 volts?Write back 1.5V (yes) or 0V (no).Cost: Complexity.UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesLast Time: 1-T DRAM cellsVddCapacitor “Word Line”“Bit Line”p-oxiden+ n+oxide------“Bit Line”Word Line and Vdd run on “z-axis”Word LineVdd“Bit Line”VddDiode leakagecurrent.Why Vcap values start out at ground.VcapUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesToday: Memory Technology Wrap-UpStatic Memory Circuits: For SRAM memory cells and for flip-flops.Memory Arrays: Row decoders, column sense amps, array sizing.DRAM Interfaces: How the SDRAM chips on the Calinx board work.CS 152 L12: Memory and Interfaces UC Regents Fall 2006 © UCBInvertersCS 152 L12: Memory and Interfaces UC Regents Fall 2006 © UCBLast Time: Model for “off” transistor ...p-n+Vd = 1Vn+Vs = Vsub = 0VdielectricVg = 0.2VVgVdVsIds I ⋲ nA n+ regionelectron energyn+ regionCurrent flows when electrons diffuse to the “gate wall” top# electrons that reach top goes up as wall comesdown, implies Ids ~exp(Vg)Ids = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]Io ~100fA, Vo = kT/q = 25mV, κ = 0.7Vg exponential dependence⋲1 if Vds > 70mVCS 152 L6: Performance UC Regents Fall 2006 © UCBLast Time: Transistor Off CurrentI dsVsVdV gI dsIoff ⋲ 10 nA0.25 ⋲ Vt1.2 mA = Ion0.7 = VddIds = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]UC Regents Fall 2006 © UCBCS 152 L12: Memory and Interfaces----------p-n+Vd = 2Vn+dielectricVg = 1V+++++++++----------Last Time: Model for “on” transistor ...Vs = Vsub = 0VI ⋲ µA VgVdVsIds Ids = (carriers in channel) / (transit time)Q = CVf(length, velocity)Ids = [(µεW)/(LD)] [Vgs -Vth] [Vds]If Vds > Vgs - Vth, channel physics change :Ids = [(µεW)/(2LD)] [Vgs -Vth]^2 W = transistor width, L = length, D = capacitor plate distance µ is velocity, ε is C dilectric constantUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesInverters: Circuits and LayoutVoutVinVdd symbolVin VoutUC Regents Fall 2006 © UCBCS 152 L12: Memory and Interfacesp-oxiden+ n+n-welloxidep+ p+ n+VoutVin VinInverter: Die Cross SectionVoutVinUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesInverters: n-fet Transistor EquationI dsVoutVinVsVdV gIf Vgs > Vt and Vds > Vgs - Vt :Ids = (k/2) (W/L) [Vgs -Vt]^2 Ids ⋲0, but really = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]Otherwise:Otherwise, if Vgs > Vt :Ids = k (W/L) [Vgs -Vt] [Vds]Note: Vt is transistor threshold, was formerly Vth. Also, Vt is actually Vt(Vs) ∼sqrt(Vs).UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesInverters: p-fet Transistor EquationVoutVinVsVdV gIf Vsg > Vt and Vsd > Vsg - Vt :Isd = (k/2) (W/L) [Vsg -Vt]^2 Isd ⋲0, but again, in reality there is a “leakage” current.Otherwise:Otherwise, if Vsg > Vt :Isd = k (W/L) [Vsg -Vt] [Vsd]Note: Vt for p-Fet and n-Fet are different. Also true for “k” (fab constant). kp < kn, due to electrons being faster than holes. I sdUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesInverters with Vin = Gnd, Vout = VddI dsVoutVinVsVdVsVdI sdIs Vsg > Vt ?Isd = k (W/L) [Vsg -Vt] [Vsd]Ids ⋲0, but really a small leakage currentIs Vsd > Vsg - Vt once Vout is Vdd?This goes as close to 0 as it can while still supplying the leakage current.UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesInverters with Vin = Vdd, Vout = GndI dsVoutVinVsVdVsVdI sdIs Vgs > Vt ?Ids = k (W/L) [Vgs -Vt] [Vds]Is Vds > Vgs - Vt once Vout is Gnd?Isd ⋲0, but really a small leakage currentThis goes as close to 0 as it can while still supplying the leakage current.UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesCalculating the inverter threshold (Vth)Assume voltage is “somewhere near the middle”For nfet, is Vds > Vgs - Vt ?For pfet, is Vsd > Vsg - Vt ?No, by definition! Use:Isd = kp (W/L) [Vdd-Vth -Vtp] [Vdd - Vth]Ids = kn (W/L) [Vth -Vtn] [Vth]To compute the exact “voltage in the middle”.I dsVoutVinVsVdVsVdI sdTie output to input.VthVthUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesQuestion: What happens when ...I dsVoutVinVsVdVsVdI sdI dsVoutVinVsVdVsVdI sdStays at Vth until a tiny amount of Vin noise appears.Then output goes to Vdd or Gnd until ...... Vin noise flips it back the other way. Lesson: at Vth, small dVin make big dVoutCS 152 L12: Memory and Interfaces UC Regents Fall 2006 © UCBStatic Memory CircuitsDynamic Memory: Circuit remembers for a fraction of a second.Non-volatile Memory: Circuit remembers for many years, even if power is off.Static Memory: Circuit remembers as long as the power is on.UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesRecall DRAM cell: 1 T + 1 C“Word Line”Bit Line“Column” “Row” Word LineVdd“Bit Line”“Row” “Column”UC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesIdea: Store each bit with its complementx “Row” Gnd Vdd Vdd Gnd We can use the redundant representation to compensate for noise and leakage.Why? xy yUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesCase #1: y = Gnd, y = Vdd ...x “Row” Gnd Vdd I dsI sdxy yUC Regents Fall 2006 © UCBCS 152 L12: Memory and InterfacesCase #2: y = Vdd, y = Gnd ...x “Row” Gnd Vdd I sdI dsxy yUC Regents Fall
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