CS 152 Computer Architecture and Engineering Lecture 12 Memory and Interfaces 2006 10 10 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Last Time Storing a Bit as Q CV State is coded as the amount of energy stored by a device 1 5V State is read by sensing the amount of energy Problems noise changes Q up or down parasitics leak or source Q Fortunately Q cannot change instantaneously but that only gets us in the ballpark CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Last Time Storing Bits Reliably Store more energy than we expect from the noise Q CV To store more charge use a bigger V or make a bigger C Cost Power chip size Example 1 bit per capacitor Represent state Write 1 5 volts on C as charge in ways that To read C measure V V 0 75 volts is a 1 are robust to noise V 0 75 volts is a 0 Cost Could have stored many bits on that capacitor Ex read C every 1 ms Correct small state errors Is V 0 75 volts that are introduced by noise Write back 1 5V Cost Complexity CS 152 L12 Memory and Interfaces yes or 0V no UC Regents Fall 2006 UCB Last Time 1 T DRAM cells Vdd Bit Line Word Line Word Line Vdd Capacitor Bit Line Bit Line n oxide n oxide pWord Line and Vdd run on z axis CS 152 L12 Memory and Interfaces Why Vcap values start out at ground Vdd Vcap Diode leakage current UC Regents Fall 2006 UCB Today Memory Technology Wrap Up Static Memory Circuits For SRAM memory cells and for flip flops Memory Arrays Row decoders column sense amps array sizing DRAM Interfaces How the SDRAM chips on the Calinx board work CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Inverters CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Last Time Model for off transistor Vg 0 2V Vd 1V I nA n dielectric p Vs Vsub 0V n Vd Vg Ids Vs Current flows Ids Io exp Vg Vs Vo 1 exp Vds Vo when electrons Vg exponential 1 if Vds 70mV diffuse to the gate wall top dependence e l e c t r o n e n e r g y electrons n region n region that reach top goes up as wall comes down implies Ids exp Vg Io 100fA Vo kT q 25mV 0 7 CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Last Time Transistor Off Current Vd Vg Ids Io exp Vg Vs Vo 1 exp Vds Vo Ids Vs Ids 1 2 mA Ion 0 25 Vt Ioff 10 nA 0 7 Vdd CS 152 L6 Performance UC Regents Fall 2006 UCB Last Time Model for on transistor Vg 1V Vd 2V I A dielectric n p Vs Vsub 0V n Vd Vg Ids Vs Ids carriers in channel transit time Q CV f length velocity Ids W LD Vgs Vth Vds If Vds Vgs Vth channel physics change Ids W 2LD Vgs Vth 2 W transistor width L length D capacitor plate distance is velocity is C dilectric constant CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Inverters Circuits and Layout Vdd symbol Vin CS 152 L12 Memory and Interfaces Vout Vin Vout UC Regents Fall 2006 UCB Inverter Die Cross Section Vout Vin n Vin oxide n p oxide p n n well p Vin CS 152 L12 Memory and Interfaces Vout UC Regents Fall 2006 UCB Inverters n fet Transistor Equation If Vgs Vt and Vds Vgs Vt Ids k 2 W L Vgs Vt 2 Vin Vd Ids Vg Vs Vout Otherwise if Vgs Vt Ids k W L Vgs Vt Vds Otherwise Ids 0 but really Io exp Vg Vs Vo 1 exp Vds Vo Note Vt is transistor threshold was formerly Vth Also Vt is actually Vt Vs sqrt Vs CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Inverters p fet Transistor Equation Vin Vg Vs Isd Vd If Vsg Vt and Vsd Vsg Vt Isd k 2 W L Vsg Vt 2 Vout Otherwise if Vsg Vt Isd k W L Vsg Vt Vsd Otherwise Isd 0 but again in reality there is a leakage current Note Vt for p Fet and n Fet are different Also true for k fab constant kp kn due to electrons being faster than holes CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Inverters with Vin Gnd Vout Vdd Is Vsd Vsg Vt once Vout is Vdd Is Vsg Vt Vin Vs Isd Vd Vd Isd k W L Vsg Vt Vsd Vout Ids This goes as close to 0 as it can while still supplying the leakage current Vs Ids 0 but really a small leakage current CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Inverters with Vin Vdd Vout Gnd Isd 0 but really a small leakage current Vs Isd Vd Vin Vd Vout This goes as close to 0 as it can while still supplying the leakage current Ids Vs Is Vds Vgs Vt once Vout is Gnd Is Vgs Vt Ids k W L Vgs Vt Vds CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Calculating the inverter threshold Vth Tie output to input Vth Vth Vin Vs Isd Vd Vd Ids Assume voltage is somewhere near the middle Vout For nfet is Vds Vgs Vt For pfet is Vsd Vsg Vt No by definition Use Vs Ids kn W L Vth Vtn Vth Isd kp W L Vdd Vth Vtp Vdd Vth To compute the exact voltage in the middle CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Question What happens when Vin Vs Isd Vd Vd Ids Vs Vout Vin Vs Isd Vd Vd Vout Ids Vs Stays at Vth until a tiny amount of Vin noise appears Then output goes to Vdd or Gnd until Vin noise flips it back the other way Lesson at Vth small dVin make big dVout CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Static Memory Circuits Dynamic Memory Circuit remembers for a fraction of a second Static Memory Circuit remembers as long as the power is on Non volatile Memory Circuit remembers for many years even if power is off CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Recall DRAM cell 1 T 1 C Word Line Row Column Bit Line Column Row Word Line Vdd Bit Line CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Idea Store each bit with its complement x x Row Why y Gnd Vdd Vdd Gnd y We can use the redundant representation to compensate for noise and leakage CS 152 L12 Memory and Interfaces UC Regents Fall 2006 UCB Case 1 y Gnd y Vdd x x Row Isd y Gnd y Vdd Ids CS 152 L12 Memory and Interfaces …
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