CS 152 Computer Architecture and Engineering Lecture 15 Virtual Memory 2005 10 20 John Lazzaro www cs berkeley edu lazzaro TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB Last Time Practical Cache Design Cache design control is done by many loosely coupled state machines including State Machine To CPU Control Control Control Addr To CPU Din Dout CS 152 L15 Virtual Memory Addr Blocks Tags Din Dout To Lower Level Memory To Lower Level Memory UC Regents Fall 2005 UCB State machines for bus control For reads your state machine must To Processor Upper Level Memory Small fast 1 sense REQ 2 latch Addr 3 create Wait 4 put Data Out on the bus Blk X From Processor Lower Level Memory Large slow Blk Y From CPU To CPU An example interface there are other possibilities CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB fou r or th e last d esired of a lon ger b u rst Th e 256Mb SDRAM u ses a p ip elin ed arch itectu re an d th erefore d oes n ot req u ire th e 2n ru le associated with a p refetch sam e b an k as sh own in Figu re 14 or each su b se READ m ay b e p erform ed to a d ifferen t b an k State machines for block fetch from DRAM DRAM can be set up to request an N byte region Figure 13 Consecut READ Burst s within region starting at anive arbitrary N k One request T0 T1 T2 T3 T4 T5 T6 CLK COM M AND READ NOP NOP NOP READ NOP NOP X 1 cycle ADDRESS BANK COL n BANK COL b DOUT n DQ CAS Lat ency 2 DOUT n 1 DOUT n 2 DOUT n 3 DOUT b Many returns T0 T1challenges T2 T3 setting T4 up correct T5 T6 State machine 1 block T7 CLK mode 2 delivering correct word direct to CPU 3 read putting all words in cache in right place CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB State machine for writeback to DRAM Figure 47 Writ e Wit h Aut o Precharge 1 T0 t CK CLK One command t CKS T1 t CL T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP NOP t CH t CKH CKE tCM S tCM H COM M AND ACTIVE NOP WRITE t CM S t CM H DQM DQM L DQM U t AS A0 A9 A11 A12 Many bytes written t AH ENABLE AUTO PRECHARGE ROW t AS BA0 BA1 COLUM N m 2 ROW t AS A10 t AH t AH BANK BANK t DS t DH DIN m DQ t RCD t DS t DH DIN m 1 t DS t DH DIN m 2 t DS t DH DIN m 3 t WR t RAS State machine challenges 1 putting cache block into correct location 2 what if a read or write wants to use DRAM before the burst is complete Must stall t RC CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB State machines to manage write buffer Solution add a write buffer to cache datapath Processor Cache Lower Level Memory Write Buffer Holds data awaiting write through to lower level memory Q Why a write buffer A So CPU doesn t stall Q Why a buffer why A Bursts of writes are not just one register common Q Are Read After Write A Yes Drain buffer RAW hazards an issue before next read or for write buffer check write buffers On reads state machine checks cache and write buffer what if word was removed from cache before lower level write On writes state machine stalls for full write buffer handles write buffer duplicates CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB Don t design one big state machine Focus on the high level state machine structure early State Machine To CPU Control Control Control Addr To CPU Din Dout CS 152 L15 Virtual Memory Addr Blocks Tags Din Dout To Lower Level Memory To Lower Level Memory UC Regents Fall 2005 UCB Today s Lecture Virtual Memory Virtual address spaces Page table layout TLB design options CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB The Limits of Physical Addressing Physical addresses of memory locations A0 A31 CPU A0 A31 Where we are in CS 152 D0 D31 Memory D0 D31 Data All programs share one address space The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB Apple II A physically addressed machine Apple 1977 CPU 1000 ns DRAM 400 ns Steve Jobs CS 152 L13 Cache I Steve Wozniak UC Regents Fall 2005 UCB The Limits of Physical Addressing Physical addresses of memory locations A0 A31 CPU A0 A31 Programming the Apple D0 D31 Memory D0 D31 Data All programs share one address space The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB Solution Add a Layer of Indirection Physical Addresses Virtual Addresses A0 A31 Virtual Physical Address Translation CPU D0 D31 A0 A31 Memory D0 D31 Data User programs run in an standardized virtual address space Address Translation hardware managed by the operating system OS maps virtual address to physical memory Hardware supports modern OS features Protection Translation Sharing CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB MIPS R4000 Address Space Model Process A ASID 12 32 2 1 Address Error 2 ASID Address Space Identifier Process A and B have independent address spaces 2 GB 32 2 1 Address Error 2 31 When Process A writes its address 9 it writes to a different physical memory location than Process B s address 9 To let Process A and B share memory OS maps parts of ASID 12 and ASID 13 to the same physical memory locations 0 ASID 13 All address spaces use a standard memory map May only be accessed by kernel supervisor 31 Process B 2 GB 0 Still works slowly if a process accesses more virtual memory than the machine has physical memory CS 152 L15 Virtual Memory UC Regents Fall 2005 UCB 4 3 System Control Coprocessor MIPS R4000 Who s Running on the CPU The System Control Cop rocessor CP0 is im p lem ented as an integral p art of the CPU and su p p orts m em ory m anagem ent ad d ress translation excep tion hand ling and other p rivileged op erations CP0 contains the registers show n in Figu re 4 7 p lu s a 48 entry TLB The sections that follow d escribe how the p rocessor u ses the m em ory m anagem ent related registers System Control Registers Each CP0 register has a u …
View Full Document
Unlocking...