UC Regents Fall 2005 © UCBCS 152 L15: Virtual Memory2005-10-20John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 15 – Virtual Memorywww-inst.eecs.berkeley.edu/~cs152/TAs: David Marquardt and Udam SainiUC Regents Fall 2005 © UCBCS 152 L15: Virtual Memory Last Time: Practical Cache DesignToCPUToLowerLevelMemoryToCPUToLowerLevelMemoryTagsBlocksAddrDinDoutAddrDinDoutState MachineControlControlControlCache design control is done by many loosely coupled state machines, including ...UC Regents Fall 2005 © UCBCS 152 L15: Virtual MemoryState machines for bus control ....Lower LevelMemoryUpper LevelMemoryTo ProcessorFrom ProcessorBlk XBlk YSmall, fast Large, slow FromCPUTo CPUFor reads,your state machine must: (1) sense REQ(2) latch Addr(3) create Wait(4) put Data Out on the bus.An example interface ... there are other possibilities.UC Regents Fall 2005 © UCBCS 152 L15: Virtual MemoryState machines for block fetch from DRAM20256M b: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change product s or specifications without not ice.256MSDRAM _G.p65 – Rev. G; Pub. 9/03 ©2003, Micron Technology, Inc.256M b: x4, x8, x16SDRAMva lid , wh ere x eq u als th e CAS la te n cy m in u s on e.This is sh own in Figure 13 for CAS laten cies of two an dth ree; d ata elem en t n + 3 is eith er th e last of a bu rst offou r or th e last desired of a lon ger bu rst. Th e 256MbSDRAM u ses a p ip elin ed arch itectu re an d th ereforedoes n ot requ ire th e 2n ru le associated with a p refetcharch itectu re. A READ com m an d can be in itiated on an yclock cycle followin g a p reviou s READ com m an d . Fu ll-sp eed ran dom read accesses can be p erform ed to th esam e ban k, as shown in Figure 14, or each sub sequ en tREAD m ay be p erform ed to a differen t b an k.Figure 13: Consecutive READ BurstsDON’T CARENOTE: Each READ command may be t o any bank. DQM is LOW. CLKDQDOUT nT2T1 T4T3 T6T5T0COMMANDADDRESSREAD NOP NOP NOP NOPBANK,COL nNOPBANK,COL bDOUTn + 1DOUTn + 2DOUTn + 3DOUT bREADX = 1 cycleCAS Latency = 2CLKDQDOUT nT2T1 T4T3 T6T5T0COMMANDADDRESSREAD NOP NOP NOP NOPBANK,COL nNOPBANK,COL bDOUTn + 1DOUTn + 2DOUTn + 3DOUT bREADNOPT7X = 2 cyclesCAS Latency = 3TRANSITIONING DATAOne request ...Many returns ...DRAM can be set up to request an N byte region starting at an arbitrary N+k within regionState machine challenges: (1) setting up correct block read mode (2) delivering correct word direct to CPU (3) putting all words in cache in right place.UC Regents Fall 2005 © UCBCS 152 L15: Virtual Memory53256M b: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change product s or specifications without notice.256MSDRAM _G.p65 – Rev. G; Pub. 9/03 ©2003, Micron Technology, Inc.256M b: x4, x8, x16SDRAMFigure 47: Writ e – Wit h Auto Precharge1NOTE: 1. For t his example, t he burst lengt h = 4.2. x16: A9, A11, and A12 = “ Don’t Care”x8: A11 and A12 = “ Don’t Care”x4: A12 = “ Don’t Care”* CAS lat ency indicat ed in parent heses.-7E -75SYM BOL* M IN M AX M IN M AX UNITStCM S 1.5 1.5 nstDH 0.8 0.8 nstDS 1.5 1.5 nstRAS 37 120,000 44 120,000 nstRC 60 66 nstRCD 15 20 nstRP 15 20 nstWR 1 CLK + 1 CLK + –7ns 7.5nsTIM ING PARAM ETERS-7E -75SYM BOL* M IN M AX M IN M AX UNITStAH 0.8 0.8 nstAS 1.5 1.5 nstCH 2.5 2.5 nstCL 2.5 2.5 nstCK (3) 7 7.5 nstCK (2) 7.5 10 nstCKH 0.8 0.8 nstCKS 1.5 1.5 nstCM H 0.8 0.8 nsENABLE AUTO PRECHARGEtCHtCLtCKtRPtRAStRCDtRCDQM/DQML, DQMUCKECLKA0-A9, A11, A12DQBA0, BA1A10tCM HtCM StAHtASROWROWBANK BANKROWROWBANKtWR DON’T CAREDIN mtDHtDSDIN m + 1 DIN m + 2 DIN m + 3COM MANDtCM HtCM SNOPNOP NOPACTIVE NOP WRITE NOP ACTIVEtAHtAStAHtAStDHtDStDHtDStDHtDStCKHtCKSNOP NOPCOLUMN m2T0 T1 T2 T4T3 T5 T6 T7 T8 T9State machine for writeback to DRAMOne command ...Many bytes writtenState machine challenges: (1) putting cache block into correct location (2) what if a read or write wants to use DRAM before the burst is complete? Must stall ...UC Regents Fall 2005 © UCBCS 152 L15: Virtual Memory State machines to manage write bufferQ. Why a write buffer ? ProcessorCacheWrite BufferLower Level MemoryHolds data awaiting write-through to lower level memoryA. So CPU doesn’t stall Q. Why a buffer, why not just one register ?A. Bursts of writes arecommon.Q. Are Read After Write (RAW) hazards an issue for write buffer?A. Yes! Drain buffer before next read, or check write buffers.Solution: add a “write buffer” to cache datapath On reads, state machine checks cache and write buffer -- what if word was removed from cache before lower-level write? On writes, state machine stalls for full write buffer, handles write buffer duplicates.UC Regents Fall 2005 © UCBCS 152 L15: Virtual Memory Don’t design one big state machine!!!ToCPUToLowerLevelMemoryToCPUToLowerLevelMemoryTagsBlocksAddrDinDoutAddrDinDoutState MachineControlControlControlFocus on the high-level state machine structure early!UC Regents Fall 2005 © UCBCS 152 L15: Virtual MemoryToday’s Lecture - Virtual MemoryVirtual address spacesPage table layoutTLB design optionsUC Regents Fall 2005 © UCBCS 152 L15: Virtual MemoryThe Limits of Physical AddressingCPU MemoryA0-A31 A0-A31D0-D31 D0-D31“Physical addresses” of memory locations DataAll programs share one address space: The physical address spaceNo way to prevent a program from accessing any machine resourceMachine language programs must beaware of the machine organization Where we are in CS 152 ...UC Regents Fall 2005 © UCBCS 152 L13: Cache IApple II: A physically addressed machine Apple ][ (1977)Steve WozniakSteve Jobs CPU: 1000 ns DRAM: 400 nsUC Regents Fall 2005 © UCBCS 152 L15: Virtual MemoryThe Limits of Physical AddressingCPU MemoryA0-A31 A0-A31D0-D31 D0-D31“Physical addresses” of memory locations DataAll programs share one address space: The physical address spaceNo way to prevent a program from accessing any machine resourceMachine language programs must beaware of the machine organization Programming the Apple ][ ...UC Regents Fall 2005 © UCBCS 152 L15: Virtual MemorySolution: Add a Layer of IndirectionCPU MemoryA0-A31 A0-A31D0-D31 D0-D31DataUser programs run in an standardizedvirtual address spaceAddress Translation hardware managed by the operating system (OS)maps virtual address to physical memory“Physical Addresses”AddressTranslationVirtual Physical“Virtual Addresses”Hardware supports “modern”
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