CS 152 Computer Architecture and Engineering Lecture 18 Real Processor Walkthru I 2004 11 02 Dave Patterson www cs berkeley edu patterson John Lazzaro www cs berkeley edu lazzaro www inst eecs berkeley edu cs152 CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Last Time A Case for RAID RAID 4 RAID 5 Original paper now on class website CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB This Week A Real Processor Walkthru Leon An open source SPARC CPU Configurable HDL designs Leon s HDL methodology CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Originally a fault tolerant CPU for the ESA Europe s NASA Now opensourced Leon may be freely used in commercial products A VHDL SPARC platform Alternati Sun RISC More than ve a CPU ISA to bus An IEEE Verilog standard peripheral popular an open s Projectwebsite website Gaisler GaislerResearch Research www gaisler com www gaisler com in EuropeProject SDRAM spec CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Leon VHDL maps to ASICs FPGAs Fabricated Fabricated ASICs ASICs Maps Maps to to Xilinx Xilinx Altera Altera Actel Actel FPGAs FPGAs CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Why use a VHDL core Configurability For For system system on on aa chip chip Example Example MP3 MP3 player player Customize Customize caches caches and and multiply divide multiply divide for for the the app app Add Add a a cocoprocessor processor specialized specialized for for CS 152 L18 Real Processor Walkthru I Only Only add add peripherals peripherals the the app app needs needs UC Regents Fall 2004 UCB Area impact of configurability 0 35 0 35 65 65 MHz MHz 40 40 mm mm Removal Removal of of FPU FPU would would reduce reduce area area power power cycle cycle CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Reality check What Sun sold in 1994 An An MP3 MP3 player player Last Last decade s decade s workstation workstation micro micro SPARC SPARC II II 85 170 85 170 MHz MHz 0 5 0 5 micron micron proces proces CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Administrivia It s Election Day Lab 4 demo on Friday in section Final report due Monday HW 4 RAID questions online a Leon question may be added soon Due Weds 11 10 5PM 283 Soda Mid Term II Tuesday 11 23 5 30 to 8 30 PM Location preference Xilinx field trip date 11 30 Details on bus transport from Soda Hall soon CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Real stuff Leon used in GPS receivers You You are are here here GPS GPS Global Global Positioning Positioning Satellite Satellite Where Where is is DoD DoD satellite satellite array array here here orbits orbits the the earth earth longitude longitude latitude latitude Handheld Handheld GPS GPS receiver receiver triangulates triangulates satellite satellite radio radio signals signals CPU CPU intensive intensive low low power power CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB GPS receiver chip uses Leon CPU CPU options options caches caches periphera periphera ls ls customiz customiz Extra Extra ed for ed for processor processor app app for for GPS GPS correlatio correlatio n n Nemerix Nemerix value add value add CS 152 L18 Real Processor Walkthru I From From antenna antenna frontfrontend end UC Regents Fall 2004 UCB Leon Customization demo CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Leon HDL Methodology CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Leon VHDL Methodology Requirements Should be easy to add new features without breaking the CPU Open source should be easy to integrate features into source tree Work with many CAD tools synthesize to many targets FPGA and ASIC Slides that follow adapted from talk by Jiri Gaisler Leon chief designer CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB 1 Entity contains two processes Combinational Combinational logic logic process process Sensitive Sensitive to to all all inputs inputs Flip flop Flip flop process process Only Only sensitive sensitive to to clock clock edge edge VHDL VHDL entity entity like like a a Verilog Verilog module module VHDL VHDL process process like like a a Verilog Verilog always always statement statement CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB 2 Naming and typing conventions The The variables variables rr and and rrinin appear appear in in every every Leon Leon entity entity VHDL VHDL for for module module and and hold hold all all register register values values VHD VHD L L CS 152 L18 Real Processor Walkthru I qqcn r and r inare are records records cn r and rin like like C C structures structures Entity Entity input input and and output output also also use use records records UC Regents Fall 2004 UCB Example A two process program Input Input state state sensitivity sensitivity Combination Combination al al process process State State record record variables variables State State process process Rationale Add new variable to record and bookkeeping is free CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Records simplify hierarchal designs VHDL VHDL Instantiati Instantiati on on CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Leon methodolody Use loops for logic for i Danger Danger The The VHDL VHDL looks looks nothing nothing like like hardware hardware Using Using HDL HDL as as algorithm algorithm description description language language CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB Conclusions Open source CPUs an alternative to licensing or designing a core uses configurability of Leon to enhance its own IP Leon s HDL methodology records combinational and state separation Differs from Berkeley style Rely on synthesis to map loops to logic CS 152 L18 Real Processor Walkthru I UC Regents Fall 2004 UCB
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