CS 152 Computer Architecture and Engineering Lecture 10 Midterm I Review Session 2006 9 28 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L10 Midterm I Review UC Regents Fall 2006 UCB 1 From last time The Break Instruction CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 2 Lab 3 ISA Specifications CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 3 MIPSASM doesn t like it CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 4 A feature not a bug Small integer Display this on Calinx Board LEDs or ModelSim output TAs need this for checkoffs useful to you too MIPSASM handles it correctly CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 5 Recall BREAK 12 l2 BEQ R0 R0 l1 l1 BEQ R0 R0 l2 BREAK 6 ID Decode EX IR WB MEM IR IR IR WE MemToReg Mux Logic op 32 A 32 A L U 32 Y wd R Addr RegFile rs1 rd1 rs2 ws Data Memory Dout Din WE M rd2 MemToReg M WE Ext CS 152 L9 Pipelining III B UC Regents Fall 2006 UCB 6 Today Midterm I Review Session HW 1 problem by problem Recall HW 1 was Fall 05 Mid term I Study tips test ground rules All questions answered almost CS 152 L10 Midterm I Review UC Regents Fall 2006 UCB 7 Points 1 10 Name 2 15 SSID 3 10 All the work is my own I have no prior knowledge of the exam contents aside from guidance from class staff I will not share the contents with others in CS152 who have not taken it yet 4 10 5 15 Signature 6 15 Please write clearly and put your name on each page Please abide by word limits Good luck 7 10 8 15 CS152 Midterm I October 4th 2005 David Marquardt Udam Saini John Lazzaro Tot 100 8 CS152 Homework I Fall 2006 Name SSID Solution Sheet Homework I is due in class on Thursday September 28 at 11 10 AM This class is the Mid term I review session Late homeworks are NOT accepted Thus if you will not be attending the review session you MUST make arrangements to hand off the homework to the instructor before classtime Homework will be graded on effort did you make an honest attempt to solve each problem not correctness We will distribute the correct answers for the homework in the review session but we will probably not return the homework you hand in until after the exam So you may wish to make a copy for reference before you hand it in This homework will count for approximately 1 5 of your final grade The homework is based on the Mid term I exam from Fall 05 You may discuss the homework problems with fellow students and the TAs but what you write down must be your own work no copying the answers from someone else s homework Good luck John Lazzaro Points 1 10 10 2 15 15 3 10 10 4 10 10 5 15 15 6 15 15 7 10 10 8 15 15 Tot 100 100 9 Part I Single Cycle CS 152 L10 Midterm I Review UC Regents Fall 2006 UCB 10 Mid term Part I ISA Single Cycle Typical Topics Points Modify a singlecycle CPU to match an unusual ISA change 1 10 2 15 3 10 Design a CPU component ex register file for a novel ISA 4 10 5 15 6 15 Analyze if a CPU design matches a proposed ISA 7 10 8 15 Write machine language for an unusual ISA CS 152 L10 Midterm I Review Tot 100 UC Regents Fall 2006 UCB 11 Mid term Part I How to do well Problem intro often features a lecture slide If you have to teach yourself that slide during the test you re starting out behind Getting the problem correct requires thinking on your feet to do a new design or analyze one given to you Just like an on site job interview CS 152 L10 Midterm I Review UC Regents Fall 2006 UCB 12 Register Design 10 points 1 Q1 Register File File Design 10 points On the top slide on the next page we show the write logic for the register file design we showed in Lecture 1 2 Redesign the write logicclk for the register file so that two registers may be written on the ws same positive clock edge The 5 bit values ws1 and ws2 specify the registers to write the 1 bit values WE1 and WE2 enable writing for each 5 R0 The constant 0 Q port 1 enabled 0 disabled and the 32 bit values wd1 and wd2 are the data to be written If both write ports are enabled and ws1 and ws2 specify R1with the valueQ wd1 the same register this register MUSTDbe En written D Draw your final design on the bottom slide shown on the next page If you E need to use a complex logic function in your answer define a truth table for a M WE En Q function f x y U below the slide and boxes on the schematic labeled D draw R2 with f x y X You may use standard symbols for simple gates OR gates AND gates multiplexers demultiplexers etc on the slide on the next page Work out your design below BEFORE drawing Only the next page will be graded D En R31 Q 32 wd 13 Q1 The actual question 1 Register File Design 10 points On the top slide on the next page we show the write logic for the register file design we showed in Lecture 1 2 Redesign the write logic for the register file so that two registers may be written on the same positive clock edge The 5 bit values ws1 and ws2 specify the registers to write the 1 bit values WE1 and WE2 enable writing for each port 1 enabled 0 disabled and the 32 bit values wd1 and wd2 are the data to be written If both write ports are enabled and ws1 and ws2 specify the same register this register MUST be written with the value wd1 Draw your final design on the bottom slide shown on the next page If you need to use a complex logic function in your answer define a truth table for a function f x y below the slide and draw boxes on the schematic labeled with f x y You may use standard symbols for simple gates OR gates AND gates multiplexers demultiplexers etc Work out your design below BEFORE drawing on the slide on the next page Only the next page will be graded CS 152 L10 Midterm I Review UC Regents Fall 2006 UCB 14 ws1 clk 5 R0 Constant 0 D Draw your answer here WE1 WE2 D Q En R1 Q En R2 Q D 5 ws2 32 wd1 En R31 Q 32 wd2 15 ws1 clk 5 WE1 R0 Constant 0 a0 a1 a2 d e m u x …
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