CS 152 L10: Midterm I Review UC Regents Fall 2006 © UCB2006-9-28John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 10 – Midterm I Review Sessionwww-inst.eecs.berkeley.edu/~cs152/TAs: Udam Saini and Jue Sun 1CS 152 L9: Pipelining III UC Regents Fall 2006 © UCBThe Break InstructionFrom last time ...2CS 152 L9: Pipelining III UC Regents Fall 2006 © UCBLab 3: ISA Specifications3CS 152 L9: Pipelining III UC Regents Fall 2006 © UCBMIPSASM doesn’t like it ???4CS 152 L9: Pipelining III UC Regents Fall 2006 © UCBSmall integer. Display this on Calinx Board LEDs or ModelSim output ... TAs need this for checkoffs, useful to you too.MIPSASM handles it correctly.A feature, not a bug ...5UC Regents Fall 2006 © UCBCS 152 L9: Pipelining IIIMux,LogicRecall ...rd1RegFilerd2WEwdrs1rs2wsExtIRIRBAM32ALU3232opIRYMIRDoutData MemoryWEDinAddrMemToRegRWE, MemToRegID (Decode) EXMEMWBBREAK 6l1: BEQ R0 R0 l2BREAK 12 l2: BEQ R0 R0 l16UC Regents Fall 2006 © UCBCS 152 L10: Midterm I ReviewToday - Midterm I Review SessionHW 1, problem by problem ...Study tips, test ground rulesAll questions answered (almost ...)Recall: HW 1 was Fall 05 Mid-term I.7CS152 Midterm IOctober 4th 2005Name:“All the work is my own. I have no prior knowledge of the exam contents, aside from guidance from class staff. I will not share the contents with others in CS152 who have not taken it yet.”Signature:Please write clearly, and put your name on each page. Please abide by word limits. Good luck!David MarquardtUdam SainiJohn Lazzaro110215310410515615710815Tot100#PointsSSID:8CS152 Homework I, Fall 2006Name:Homework I is due in class on Thursday September 28 at 11:10 AM.This class is the Mid-term I review session.Late homeworks are NOT accepted. Thus, if you will not be attendingthe review session, you MUST make arrangements to hand off thehomework to the instructor before classtime.Homework will be graded on effort (did you make an honest attempt tosolve each problem?), not correctness. We will distribute the correctanswers for the homework in the review session, but we will probablynot return the homework you hand in until after the exam. So, you may wish to make a copy for reference before you hand it in.This homework will count for approximately 1.5% of your final grade.The homework is based on the Mid-term I exam from Fall 05.You may discuss the homework problems with fellow students and the TAs, but what you write down must be your own work (no copying the answers from someone else’s homework). Good luck! John LazzaroSSID:1101021515310104101051515615157101081515Tot100100#PointsSolution Sheet9CS 152 L10: Midterm I Review UC Regents Fall 2006 © UCBPart I - Single Cycle10CS 152 L10: Midterm I Review UC Regents Fall 2006 © UCBMid-term, Part I: ISA & Single Cycle110215310410515615710815Tot100#PointsDesign a CPU component (ex: register file) for a novel ISA.Analyze if a CPU design matches a proposed ISA.Write machine language for an unusual ISA.Modify a single-cycle CPU to match an unusual ISA change. Typical Topics11CS 152 L10: Midterm I Review UC Regents Fall 2006 © UCBMid-term, Part I: How to do well ...Problem intro often features a lecture slide. If you have to teach yourself that slide during the test, you’re starting out behind.Getting the problem correct requires thinking on your feet to do a new design or analyze one given to you.Just like an on-site job interview ...12R1R2...R31QQQR0 - The constant 0 QclkwdDDDEnEnEnDEMUX...ws5WE32Q1. Register File Design (10 points)1 Register File Design (10 points)On the top slide on the next page, we show the write logic for the register filedesign we showed in Lecture 1-2.Redesign the write logic for the register file, so that two registe rs may bewritten on the same positive clock edge. The 5-bit values ws1 and ws2 specifythe registers to write, the 1-bit values WE1 and WE2 enable writing for eachport (1 = enabled, 0 = disabled), and the 32-bit values wd1 and wd2 are thedata to be written. If both write ports are enabled, and ws1 and ws2 specifythe same register, this register MUST be written with the value wd1.Draw your final design on the bottom slide shown on the next page. If youneed to use a complex logic function in your answer, define a truth table for afunction f(x, y, . . .) below the slide, and draw boxes on the schematic labeledwith f(x, y, . . .). You may use standard symbols for simple gates (OR gates,AND gates, multiplexers, demultiplexers, etc).Work out your design below BEFORE drawing on the slide on the next page.Only the next page will be graded.13CS 152 L10: Midterm I Review UC Regents Fall 2006 © UCBQ1: The actual question ...1 Register File Design (10 points)On the top slide on the next page, we show the write logic for the register filedesign we showed in Lecture 1-2.Redesign the write logic for the re gister file, so that two registe rs may bewritten on the same positive clock edge. The 5-bit values ws1 and ws2 specifythe registers to write, the 1-bit values WE1 and WE2 enable writing for eachport (1 = enabled, 0 = disabled), and the 32-bit values wd1 and wd2 are thedata to be written. If both write ports are enabled, and ws1 and ws2 specifythe same register, this register MUST be written with the value wd1.Draw your final design on the bottom slide shown on the next page. If youneed to use a complex logic function in your answer, define a truth table for afunction f(x, y, . . .) below the slide, and draw boxes on the schematic labeledwith f(x, y, . . .). You may use standard symbols for simple gates (OR gates,AND gates, multiplexers, demultiplexers, etc).Work out your design below BEFORE drawing on the slide on the next page.Only the next page will be graded.14R1R2...R31QR0 - Constant 0Qclkwd1DDDEnEnEnws15WE132wd232ws25WE2QQDraw your answer here ...15R1R2...R31QR0 - Constant 0Qclkwd1DDDEnEnEn32wd232QQws15WE1demuxa0a1a2a31...ws25WE2demuxb0b1b2b31...013201320132a2b2a31b31a1b1ororor16CS 152 L10: Midterm I Review UC Regents Fall 2006 © UCBQ2: Single Cycle Design (part A)2 Single Cycle Design (15 points)Below, we show a slightly-modified version of the single-cycle datapath that wederived in the first weeks of class. On the following pages, we ask questionsabout this design.Clk32Addr DataInstrMem32DPCQ3232+32320x4PCSrc32+32Extimm Note: imm is immediate field from I- format bitfield. Ext unit sign extends, does word->byte shift.BRSrcrd1 Note: rd1 is output from register file. Single-cycle
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