CS 152 Computer Architecture and Engineering Lecture 17 Vector Computers Krste Asanovic Electrical Engineering and Computer Sciences University of California Berkeley http www eecs berkeley edu krste http inst cs berkeley edu cs152 Recap VLIW In a classic VLIW compiler is responsible for avoiding all hazards simple hardware complex compiler Later VLIWs added more dynamic hardware interlocks Use loop unrolling and software pipelining for loops trace scheduling for more irregular code Static scheduling difficult in presence of unpredictable branches and variable latency memory VLIWs somewhat successful in embedded computing no clear success in general purpose computing despite several attempts Static scheduling compiler techniques also useful for superscalar processors 4 8 2008 CS152 Spring 08 2 Supercomputers Definition of a supercomputer Fastest machine in world at given task A device to turn a compute bound problem into an I O bound problem Any machine costing 30M Any machine designed by Seymour Cray CDC6600 Cray 1964 regarded as first supercomputer 4 8 2008 CS152 Spring 08 3 Supercomputer Applications Typical application areas Military research nuclear weapons cryptography Scientific research Weather forecasting Oil exploration Industrial design car crash simulation Bioinformatics Cryptography All involve huge computations on large data sets In 70s 80s Supercomputer Vector Machine 4 8 2008 CS152 Spring 08 4 Vector Supercomputers Epitomized by Cray 1 1976 Scalar Unit Load Store Architecture Vector Extension Vector Registers Vector Instructions Implementation Hardwired Control Highly Pipelined Functional Units Interleaved Memory System No Data Caches No Virtual Memory 4 8 2008 5 CS152 Spring 08 Cray 1 1976 64 Element Vector Registers Single Port Memory 16 banks of 64 bit words 8 bit SECDED Ah j k m A0 80MW sec data load store Tjk Ah j k m A0 320MW sec instruction buffer refill 64 T Regs Si 64 B Regs Ai Bjk memory bank cycle 50 ns S0 S1 S2 S3 S4 S5 S6 S7 A0 A1 A2 A3 A4 A5 A6 A7 NIP 64 bitx16 4 Instruction Buffers 4 8 2008 V0 V1 V2 V3 V4 V5 V6 V7 Vi V Mask Vj V Length Vk FP Add Sj FP Mul Sk FP Recip Si Int Add Int Logic Int Shift Pop Cnt Aj Ak Ai Addr Add Addr Mul CIP LIP processor cycle 12 5 ns 80MHz CS152 Spring 08 6 Vector Programming Model Scalar Registers r15 v15 r0 v0 Vector Registers 0 1 2 VLRMAX 1 Vector Length Register Vector Arithmetic Instructions ADDV v3 v1 v2 v1 v2 v3 Vector Load and Store Instructions LV v1 r1 r2 Base r1 4 8 2008 VLR 0 1 v1 VLR 1 Vector Register Memory Stride r2 CS152 Spring 08 7 Vector Code Example Scalar Code Vector Code C code LI R4 64 LI VLR 64 for i 0 i 64 i LV V1 R1 C i A i B i loop L D F0 0 R1 LV V2 R2 L D F2 0 R2 ADDV D V3 V1 V2 ADD D F4 F2 F0 SV V3 R3 S D F4 0 R3 DADDIU R1 8 DADDIU R2 8 DADDIU R3 8 DSUBIU R4 1 BNEZ R4 loop 4 8 2008 CS152 Spring 08 8 Vector Instruction Set Advantages Compact one short instruction encodes N operations Expressive tells hardware that these N operations are independent use the same functional unit access disjoint registers access registers in same pattern as previous instructions access a contiguous block of memory unit stride load store access memory in a known pattern strided load store Scalable can run same code on more parallel pipelines lanes 4 8 2008 9 CS152 Spring 08 Vector Arithmetic Execution Use deep pipeline fast clock to execute element operations Simplifies control of deep pipeline because elements in vector are independent no hazards V 1 V 2 V 3 Six stage multiply pipeline V3 v1 v2 4 8 2008 CS152 Spring 08 10 Vector Instruction Execution ADDV C A B Execution using one pipelined functional unit Execution using four pipelined functional units A 6 B 6 A 24 B 24 A 25 B 25 A 26 B 26 A 27 B 27 A 5 B 5 A 20 B 20 A 21 B 21 A 22 B 22 A 23 B 23 A 4 B 4 A 16 B 16 A 17 B 17 A 18 B 18 A 19 B 19 A 3 B 3 A 12 B 12 A 13 B 13 A 14 B 14 A 15 B 15 4 8 2008 C 2 C 8 C 9 C 10 C 11 C 1 C 4 C 5 C 6 C 7 C 0 C 0 C 1 C 2 C 3 11 CS152 Spring 08 Vector Memory System Cray 1 16 banks 4 cycle bank busy time 12 cycle latency Bank busy time Cycles between accesses to same bank Base Stride Vector Registers Address Generator 0 1 2 3 4 5 6 7 8 9 A B C D E F Memory Banks 4 8 2008 CS152 Spring 08 12 Vector Unit Structure Functional Unit Vector Registers Elements 0 4 8 Elements 1 5 9 Elements 2 6 10 Elements 3 7 11 Lane Memory Subsystem 4 8 2008 13 CS152 Spring 08 T0 Vector Microprocessor UCB ICSI 1995 Lane Vector register elements striped over lanes 24 25 26 27 28 16 17 18 19 20 8 9 10 11 12 0 1 2 3 4 4 8 2008 CS152 Spring 08 29 30 31 21 22 23 13 14 15 5 6 7 14 Vector Instruction Parallelism Can overlap execution of multiple vector instructions example machine has 32 elements per vector register and 8 lanes Load Unit load Multiply Unit Add Unit mul add time load mul add Instruction issue Complete 24 operations cycle while issuing 1 short instruction cycle 4 8 2008 CS152 Spring 08 15 CS152 Administrivia Wednesday section 9 30 10 30AM PS4 review Thursday quiz covers L12 L15 PS4 Lab 4 4 8 2008 CS152 Spring 08 16 Vector Chaining Vector version of register bypassing introduced with Cray 1 LV V 1 v1 V 2 V 3 V 4 V 5 MULV v3 v1 v2 ADDV v5 v3 v4 Chain Load Unit Chain Mult Add Memory 4 8 2008 17 CS152 Spring 08 Vector Chaining Advantage Without chaining must wait for last element of result to be written before starting dependent instruction Load Mul Time Add With chaining can start dependent instruction as soon as first result appears Load Mul Add 4 8 2008 CS152 Spring 08 18 Vector Startup Two components of vector startup penalty functional unit latency time through pipeline dead time or recovery time time before another vector instruction can start down pipeline Functional Unit Latency R X X X W R X X X W R X X X W R X X X W R X X X W R X X X W R X X X W R X X X W R X X X W R X X X First Vector Instruction Dead Time 4 8 2008 Dead Time Second Vector Instruction W 19 CS152 Spring 08 Dead Time and Short Vectors No dead time 4 cycles dead time T0 Eight lanes No dead time 100 …
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