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Berkeley COMPSCI 152 - Lecture 23 – Buses, Disks, and RAID

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UC Regents Spring 2005 © UCBCS 152 L23: Buses, Disks, and RAID2005-4-14John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 23 – Buses, Disks, and RAIDwww-inst.eecs.berkeley.edu/~cs152/TAs: Ted Hong and David MarquardtUC Regents Spring 2005 © UCBCS 152 L23: Buses, Disks, and RAIDLast Time: Multithreading, Multiple Coressupports a 1.875-Mbyte on-chip L2 cache.Power4 and Power4+ systems both have 32-Mbyte L3 caches, whereas Power5 systemshave a 36-Mbyte L3 cache.The L3 cache operates as a backdoor withseparate buses for reads and writes that oper-ate at half processor speed. In Power4 andPower4+ systems, the L3 was an inline cachefor data retrieved from memory. Because ofthe higher transistor density of the Power5’s130-nm technology, we could move the mem-ory controller on chip and eliminate a chippreviously needed for the memory controllerfunction. These two changes in the Power5also have the significant side benefits of reduc-ing latency to the L3 cache and main memo-ry, as well as reducing the number of chipsnecessary to build a system.Chip overviewFigure 2 shows the Power5 chip, whichIBM fabricates using silicon-on-insulator(SOI) devices and copper interconnect. SOItechnology reduces device capacitance toincrease transistor performance.5Copperinterconnect decreases wire resistance andreduces delays in wire-dominated chip-tim-ing paths. In 130 nm lithography, the chipuses eight metal levels and measures 389 mm2.The Power5 processor supports the 64-bitPowerPC architecture. A single die containstwo identical processor cores, each supportingtwo logical threads. This architecture makesthe chip appear as a four-way symmetric mul-tiprocessor to the operating system. The twocores share a 1.875-Mbyte (1,920-Kbyte) L2cache. We implemented the L2 cache as threeidentical slices with separate controllers foreach. The L2 slices are 10-way set-associativewith 512 congruence classes of 128-byte lines.The data’s real address determines which L2slice the data is cached in. Either processor corecan independently access each L2 controller.We also integrated the directory for an off-chip 36-Mbyte L3 cache on the Power5 chip.Having the L3 cache directory on chip allowsthe processor to check the directory after anL2 miss without experiencing off-chip delays.To reduce memory latencies, we integratedthe memory controller on the chip. This elim-inates driver and receiver delays to an exter-nal controller.Processor coreWe designed the Power5 processor core tosupport both enhanced SMT and single-threaded (ST) operation modes. Figure 3shows the Power5’s instruction pipeline,which is identical to the Power4’s. All pipelinelatencies in the Power5, including the branchmisprediction penalty and load-to-use laten-cy with an L1 data cache hit, are the same asin the Power4. The identical pipeline struc-ture lets optimizations designed for Power4-based systems perform equally well onPower5-based systems. Figure 4 shows thePower5’s instruction flow diagram.In SMT mode, the Power5 uses two sepa-rate instruction fetch address registers to storethe program counters for the two threads.Instruction fetches (IF stage) alternatebetween the two threads. In ST mode, thePower5 uses only one program counter andcan fetch instructions for that thread everycycle. It can fetch up to eight instructionsfrom the instruction cache (IC stage) everycycle. The two threads share the instructioncache and the instruction translation facility.In a given cycle, all fetched instructions comefrom the same thread.42HOTCHIPS15IEEE MICROFigure 2. Power5 chip (FXU = fixed-point execution unit, ISU= instruction sequencing unit, IDU = instruction decode unit,LSU = load/store unit, IFU = instruction fetch unit, FPU =floating-point unit, and MC = memory controller).(2) Threads on two cores share memory via L2 cache operations.Much faster than2 CPUs on 2 chips.(1) Threads on two cores that use shared libraries conserve L2 memory.UC Regents Spring 2005 © UCBCS 152 L23: Buses, Disks, and RAIDToday: Buses, Disks, and RAIDBuses: Shared physical wires that act to communicate signals between several devices (often ”peripherals”)Disks: Store bits as the orientation of miniature “bar magnets” on a rotating platter. A mechanical device: slow and prone to failure.Buses let computers be expandable: add more memory, a better graphics card, a webcam, etc.UC Regents Spring 2005 © UCBCS 152 L23: Buses, Disks, and RAIDProperties of bus structures ...20256Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specificat ions without notice.256MSDRAM _G.p65 – Rev. G; Pub. 9/03 ©2003, Micron Technology, Inc.256M b: x4, x8, x16SDRAMvalid, where x equals th e CAS laten cy m inus on e.Th is is sh own in Figure 13 for CAS laten cies of two an dthree; data elem en t n + 3 is eith er the last of a burst offou r or th e last desired of a lon ger burst. The 256MbSDRAM uses a pip elin ed architecture an d thereforedoes n ot requ ire the 2n ru le associated with a p refetcharchitecture. A READ com m an d can be in itiated on an yclock cycle followin g a previous READ com m an d. Fu ll-speed ran dom read accesses can be p erform ed to thesam e ban k, as sh own in Figu re 14, or each subsequ en tREAD m ay be p erform ed to a differen t ban k.Figure 13: Consecutive READ Burst sDON’T CARENOTE: Each READ command may be t o any bank. DQM is LOW. CLKDQDOUT nT2T1 T4T3 T6T5T0COMMANDADDRESSREAD NOP NOP NOP NOPBANK,COL nNOPBANK,COL bDOUTn + 1DOUTn + 2DOUTn + 3DOUT bREADX = 1 cycleCAS Latency = 2CLKDQDOUT nT2T1 T4T3 T6T5T0COMMANDADDRESSREAD NOP NOP NOP NOPBANK,COL nNOPBANK,COL bDOUTn + 1DOUTn + 2DOUTn + 3DOUT bREADNOPT7X = 2 cyclesCAS Latency = 3TRANSITIONING DATAControl lines: Controls transactions, signals what is on data linesData lines: Carries information across the interfaceBuses are an abstraction for communication: helps designers compose large, complex systems.UC Regents Spring 2005 © UCBCS 152 L23: Buses, Disks, and RAIDBuses are defined in layers ...Transaction ProtocolsSignal Timing on WiresWiresElectrical PropertiesMechanical Properties116 VSS117 A1118 A3119 A5120 A7121 A9122 A11123 A13124 VDD125 CK1126 A12127 VSS128 CKE0129 S3130 DQMB6131 DQMB7132 A13133 VDD134 NC CB14135 NC CB15136 NC CB6137 NC CB7138 VSS139 DQ48140 DQ49141 DQ50142 DQ51143 VDD144 DQ52145 NC, MIRQ146 VREF, NC147 NC148


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Berkeley COMPSCI 152 - Lecture 23 – Buses, Disks, and RAID

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