CS 152 Computer Architecture and Engineering Lecture 23 Buses Disks and RAID 2005 4 14 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L23 Buses Disks and RAID UC Regents Spring 2005 UCB 1 Threads on two cores that use shared libraries conserve L2 memory 2 Threads on two cores share memory via L2 cache operations Much faster than 2 CPUs on 2 chips CS 152 L23 Buses Disks and RAID supports a 1 875 Mbyte on chip L2 cache Power4 and Power4 systems both have 32Mbyte L3 caches whereas Power5 systems have a 36 Mbyte L3 cache The L3 cache operates as a backdoor with separate buses for reads and writes that oper Figure 2 Power5 chip FXU fixed point execution unit ISU instruction sequencing unit IDU instruction decode unit LSU load store unit IFU instruction fetch unit FPU floating point unit and MC memory controller ing p uses T Powe two i two l the c tipro cores cach ident each with The slice t can i W chip Havi the p L2 m To r the inate nal c W supp threa show whic Proc Last Time Multithreading Multiple Cores UC Regents Spring 2005 UCB Today Buses Disks and RAID Buses Shared physical wires that act to communicate signals between several devices often peripherals Buses let computers be expandable add more memory a better graphics card a webcam etc Disks Store bits as the orientation of miniature bar magnets on a rotating platter A mechanical device slow and prone to failure CS 152 L23 Buses Disks and RAID UC Regents Spring 2005 UCB fou r or th e last d esired of a lon ger b u rst Th e 256Mb SDRAM u ses a p ip elin ed arch itectu re an d th erefore d oes n ot req u ire th e 2n ru le associated with a p refetch sam e b an k as sh own in Figu re 14 or ea READ m ay b e p erform ed to a d ifferen t Properties of bus structures Control lines Controls transactions signalsive what is on data Figure 13 Consecut READ Burst s lines T0 T1 T2 T3 T4 T5 T6 CLK COM M AND READ NOP NOP NOP READ NOP NOP X 1 cycle ADDRESS BANK COL n BANK COL b DOUT n DQ DOUT n 2 DOUT n 1 DOUT n 3 DOUT b CAS Lat ency 2 Data lines Carries information across the interface T0 T1 T2 T3 T4 T5 T6 T7 Buses are an abstraction for communication helps designers compose large complex systems CLK CS 152 L23 Buses Disks and RAID UC Regents Spring 2005 UCB Buses are defined in layers VSS 32 116 VSS A0 33 117 A1 A2 34 118 A3 A4 35 119 A5 A6 36 120 A7 A8 37 121 A9 A10 38 X72 ECC MODE DIMM 122 A11 A12 39 A13 40 X64 DIMM 123 VDD 124 VDD VDD 41 125 CK1 CK0 42 126 A12 VSS 43 127 VSS NU 44 128 CKE0 S2 45 DQMB2 X80 ECC MODE DIMM FRONT SIDE REAR SIDE 129 S3 46 130 DQMB6 DQMB3 47 131 DQMB7 NU 48 132 A13 JEDEC Standard No 21 C Page 4 5 4 3 Example DIMM DRAM bus The name of every wire is defined in a standards document Transaction Protocols VDD 49 133 VDD CB10 NC 50 134 NC CB11 NC 51 135 NC CB2 NC 52 136 NC CB6 CB3 NC 53 137 NC CB7 VSS 54 138 VSS DQ16 55 139 DQ48 DQ17 56 140 DQ49 DQ18 57 141 DQ50 DQ19 58 142 DQ51 VDD 59 143 VDD DQ20 60 144 DQ52 NC MWAIT 61 145 NC MIRQ VREF NC 62 146 VREF NC CKE1 63 147 NC VSS 64 148 VSS DQ21 65 149 DQ53 DQ22 66 150 DQ54 DQ23 67 151 DQ55 VSS 68 152 VSS DQ24 69 153 DQ56 DQ25 70 154 DQ57 DQ26 71 155 DQ58 DQ27 72 156 DQ59 VDD 73 157 VDD DQ28 74 158 DQ60 DQ29 75 159 DQ61 DQ30 76 160 DQ62 DQ31 77 161 DQ63 VSS 78 162 VSS CK2 79 163 CK3 NC 80 164 NC NC 81 165 SA0 SDA 82 166 SA1 SCL 83 167 SA2 VDD 84 168 VDD CS 152 L23 Buses Disks and RAID CB14 CB15 Signal Timing on Wires Wires Electrical Properties Mechanical Properties JEDEC Joint Electron Device Engineering Council Makes the DRAM bus standards UC Regents Spring 2005 UCB by loading them with exactly four SDRAM loads Clock signals must have either four SDRAM loads or cial attention must be given to the routing of the SDRAM clock signal s to ensure adequate signal they must be terminated into 10 ohms and 10 pF Trace lengths to the RC termination of unloaded clocks ity rise fall time minimum skew between clock edges at each SDRAM component and predictable must be kept to an absolute minimum Clock traces must be 5 mils wide with 15 mil spacing to any other w to motherboard chipset clocks For that reason all utilized clocks are made to look electrically similar signal including the clocks themselves oading them with exactly four SDRAM loads Clock signals must have either four SDRAM loads or must be terminated into 10 ohms and 10 pF Trace lengths to the RC termination of unloaded clocks SDRAM minimum Clock traces must be 5 mils wide with 15 mil spacing to any other t be kept to an absolute Pin Loaded al including the clocks themselves L2 L4 L3 Lower levels of DRAM bus specification Clock SDRAM SDRAM Pin Pin L4 SDRAM Pin SDRAM L4 Pin SDRAM SDRAM Pin Pin L4 SDRAM Pin L4 L3 L3 L2 L3 L4 L3 L1 L1 L2 L4 L3 L3 Loaded Clock L3 Transaction Protocols SO DIMM Connector L0 Unloaded SO DIMM Clock SO DIMM Connector Connector Signal Timing on Wires Unloaded10 Ohm Clock SO DIMM 10 Connector pF L2 L4 L0 10 Ohm 10 pF Stuff for Unloaded Clock Wires 133 MHz PC SDRAM Unbuffered SO DIMM Specification 1 0 Introduction Stuff for Note Either the L2 or the L3 trace segment may contain oneUnloaded additional via which is not shown in the diagram Clock Electrical Properties Figure 11 Signal routing topologies for Clocks Thisis specification defines the electrical mechanical and trace routing requirements fo Note Either the L2 or the L3 trace segment may contain one additional via which not shown in the diagram Table 9 Trace Length Table for Clock Topologies 133 MHz 64 bit wide non ECC Parity 2 clock unbuffered Synchronous DRAM Sm Mechanical Properties Line Memory Modules SDRAM SO DIMMs These SDRAM SO DIMMs are inten in personal notebook computer motherboards Figure routing topologies for Clocks Segment L0 11 Signal L1 L2 L3 L4 Total Min Total Max memory installed Length 0 10 1 00 0 80 0 50 0 10 2 45 2 55 Table 9 Trace Length Table for Clock Topologies Tolerance 0 05 0 02 0 02 0 02 0 05 Layer L0 Outer Inner Inner Inner Outer ment L1 L2 L3 …
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