Review Elements of the Design Process Divide and Conquer e g ALU Formulate a solution in terms of simpler components CS152 Computer Architecture and Engineering Lecture 6 Multiply Divide Shift Design each of the components subproblems Generate and Test e g ALU Given a collection of building blocks look for ways of putting them together that meets requirement Successive Refinement e g multiplier divider Solve most of the problem i e ignore some constraints or special cases examine and correct shortcomings February 12 2003 Formulate High Level Alternatives e g shifter John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 2 12 03 CS152 Kubiatowicz Lec6 1 UCB Spring 2003 Review ALU Design Articulate many strategies to keep in mind while pursuing any one approach Work on the Things you Know How to Do The unknown will become obvious as you make progress 2 12 03 CS152 Kubiatowicz Lec6 2 UCB Spring 2003 Review Carry Look Ahead Design trick peek C0 Cin A 0 0 1 1 Bit slice plus extra on the two ends Overflow means number too large for the representation A0 Carry look ahead and other adder tricks B0 A 32 B S C1 G0 C0 x P0 32 A1 signed arith and cin xor co B1 G P S C out 0 C in C in 1 kill propagate propagate generate G A and B P A xor B C2 G1 G0 x P1 C0 x P0 x P1 a31 a0 b31 b0 ALU0 co cin s0 ALU31 co cin s31 Ovflw 32 S 2 12 03 G P B 0 1 0 1 UCB Spring 2003 4 A2 M C L to produce select comp c in CS152 Kubiatowicz Lec6 3 B2 G P S C3 G2 G1 x P2 G0 x P1 x P2 C0 x P0 x P1 x P2 A3 B3 G P S G P C4 2 12 03 UCB Spring 2003 CS152 Kubiatowicz Lec6 4 Review Design Trick Guess or Precompute CP 2n 2 CP n n bit adder Review Carry Skip Adder reduce worst case delay B A4 n bit adder B A0 4 bit Ripple Adder P3 CP 2n CP n CP mux n bit adder 1 n bit adder 0 P2 P1 4 bit Ripple Adder S P3 P0 P2 P1 S P0 n bit adder Just speed up the slowest case for each block Exercise optimal design uses variable block sizes Carry select adder Cout 2 12 03 UCB Spring 2003 CS152 Kubiatowicz Lec6 5 MIPS arithmetic instructions Instruction add subtract add immediate add unsigned subtract unsigned add imm unsign multiply multiply unsigned divide Example add 1 2 3 sub 1 2 3 addi 1 2 100 addu 1 2 3 subu 1 2 3 addiu 1 2 100 mult 2 3 multu 2 3 div 2 3 Meaning 1 2 3 1 2 3 1 2 100 1 2 3 1 2 3 1 2 100 Hi Lo 2 x 3 Hi Lo 2 x 3 Lo 2 3 divide unsigned divu 2 3 Lo 2 3 Move from Hi Move from Lo mfhi 1 mflo 1 1 Hi 1 Lo 2 12 03 UCB Spring 2003 CS152 Kubiatowicz Lec6 6 MULTIPLY unsigned Comments 3 operands exception possible 3 operands exception possible constant exception possible 3 operands no exceptions 3 operands no exceptions constant no exceptions 64 bit signed product 64 bit unsigned product Lo quotient Hi remainder Hi 2 mod 3 Unsigned quotient remainder Hi 2 mod 3 Used to get copy of Hi Used to get copy of Lo Paper and pencil example unsigned Multiplicand Multiplier Product 1000 1001 1000 0000 0000 1000 01001000 m bits x n bits m n bit product Binary makes it easy 0 place 0 0 x multiplicand 1 place a copy 1 x multiplicand 4 versions of multiply hardware algorithm successive refinement 2 12 03 UCB Spring 2003 CS152 Kubiatowicz Lec6 7 2 12 03 UCB Spring 2003 CS152 Kubiatowicz Lec6 8 Unsigned Combinational Multiplier 0 0 A3 How does it work 0 A2 0 0 A1 0 0 0 A3 A0 0 0 A2 A1 0 A0 B0 B0 A3 A3 A3 A2 A2 A1 A1 A0 B1 A3 A0 A3 B2 A3 P7 P6 A2 A1 P5 P7 A0 P4 P6 A2 A2 A1 P5 P4 A2 A1 A1 A0 B1 A0 B2 A0 P3 B3 P2 P1 P0 B3 P3 P2 P1 At each stage shift A left x 2 P0 Use next bit of B to determine whether to add in shifted multiplicand Stage i accumulates A 2 i if Bi 1 Accumulate 2n bit partial product at each stage Q How much hardware for 32 bit multiplier Critical path 2 12 03 CS152 Kubiatowicz Lec6 9 UCB Spring 2003 C2 B 2 A 2 A2A1A0 B2B1B0 C2C1C0 D2D1D0 I1 I2 C 1 B1 A1 I3 I1 Carry Save Adder 3 2 S4S3S2S1S0 S1 Add Columns first then rows S0 Example 53 bit multiply for floating point At least 53 levels with na ve technique Only 9 with Carry save addition I1 I1 I2 I3 S1 S0 S1 I1 I2 S1 64 bit Multiplicand reg 64 bit ALU 64 bit Product reg 32 bit multiplier reg I3 S0 D0 I3 I2 Shift Left Multiplicand 64 bits 0 I1 Carry Save Adder 3 2 S0 I2 Carry Save Adder 3 2 D1 I3 Carry Save Adder 3 2 S0 S1 Multiplier S0 64 bit ALU Shift Right 32 bits 0 I1 I2 I3 Carry Save Adder 3 2 S1 I1 I2 I3 Carry Save Adder 3 2 S0 S4 S3 2 12 03 I3 S1 Carry Save Adder 3 2 Can be used to reduce critical path of multiply I2 C 0 B0 A0 Carry Save Adder 3 2 D2 Full Adder 3 2 element CS152 Kubiatowicz Lec6 10 UCB Spring 2003 Unisigned shift add multiplier version 1 Carry Save addition of 4 integers Adding 2 12 03 UCB Spring 2003 S1 S0 S2 I1 I2 I3 Product Carry Save Adder 3 2 S1 Control 64 bits S0 S1 Write Multiplier datapath control S0 CS152 Kubiatowicz Lec6 11 2 12 03 UCB Spring 2003 CS152 Kubiatowicz Lec6 12 Multiply Algorithm Version 1 Multiplier0 1 Observations on Multiply Version 1 Start 1 Test Multiplier0 Multiplier0 0 1 2 bits in multiplicand always 0 64 bit adder is wasted 1a Add multiplicand to product place the result in Product register 1 2 3 1 2 3 Product Multiplier Multiplicand 0000 0000 0011 0000 0010 2 Shift the Multiplicand register left 1 bit 0000 0010 0011 0000 0010 0000 0010 0011 0000 0100 3 Shift the Multiplier register right 1 bit 0000 0010 0001 0000 0100 0000 0110 0001 0000 0100 0000 0110 0001 0000 1000 32nd No 32 repetitions 0000 0110 0000 0000 1000 repetition 0000 0110 0000 0000 1000 2 12 03 UCB Spring 2003 1 clock per cycle 100 clocks per multiply Ratio of multiply to add 5 1 to 100 1 Yes 32 repetitions CS152 Kubiatowicz Done Lec6 13 MULTIPLY HARDWARE Version 2 0 s inserted in right of multiplicand as shifted least significant bits of …
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