CS 152 Computer Architecture and Engineering Lecture 9 Pipelining III Cong r at s 2006 9 26 on L ab 2 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 1 Recall First Lecture Sti Our goal for Fall 06 ll o nt ra c k All projects successful We want every group to get every CPU working CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB 2 Last time A Hazard Taxonomy Structural Hazards Data Hazards RAW WAR WAW Control Hazards taken branches and jumps On each clock cycle we must detect the presence of all of these hazards and resolve them before they break the contract with the programmer CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 3 Last Time Hazard Resolution Toolkit Stall earlier instructions in pipeline Forward results computed in later pipeline stages to earlier stages Add new hardware or rearrange hardware design to eliminate hazard Change ISA to eliminate hazard Kill earlier instructions in pipeline Make hardware handle concurrent requests to eliminate hazard CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 4 Today Putting it All Together Specifications for Lab 3 At risk hazards for Lab 3 Preferred hazard resolution tools Tips for control design CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 5 Lab 3 ISA Specifications Single delay slot No load delay slot CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 6 Remember Online MIPS documentation The level of detail needed for a pipelined design can only be found in this document CS 152 L9 Pipelining III AND And AND 31 26 25 SPECIAL 000000 6 Format 21 20 16 15 11 10 rs rt rd 5 5 5 AND rd rs rt 6 5 0 0 AND 00000 100100 5 6 MIPS32 Purpose To do a bitwise logical AND Description rd rs AND rt The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation The result is placed into GPR rd Restrictions None Operation GPR rd GPR rs and GPR rt Exceptions None UC Regents Fall 2006 UCB 7 Hazard Diagnosis CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 8 Data Hazards Read After Write Read After Write RAW hazards Instruction I2 expects to read a data value written by an earlier instruction but I2 executes too early and reads the wrong copy of the data Lab 3 solution use forwarding heavily fall back on stalling when forwarding won t work or slows down the critical path too much CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 9 Full bypass network ID Decode EX IR WB MEM IR IR IR WE MemToReg From WB Mux Logic op 32 A 32 A L U 32 Y wd R Addr RegFile rs1 rd1 rs2 ws Data Memory Dout Din WE M rd2 MemToReg M WE Ext CS 152 L9 Pipelining III B UC Regents Fall 2006 UCB 10 Common bug Multiple forwards OR R2 R3 R1 AND R2 R2 R1 ADD R4 R3 R2 Which do we forward from ID Decode EX IR WB MEM IR IR IR WE MemToReg From WB Mux Logic op 32 A 32 A L U 32 Y wd R Addr RegFile rs1 rd1 rs2 ws Data Memory Dout Din WE M rd2 MemToReg M WE Ext CS 152 L9 Pipelining III B UC Regents Fall 2006 UCB 11 Data Hazards WAR and WAW Write After Read WAR hazards Instruction I2 expects to write over a data value after an earlier instruction I1 reads it But instead I2 writes too early and I1 sees the new value Write After Write WAW hazards Instruction I2 writes over data an earlier instruction I1 also writes But instead I1 writes after I2 and the final data value is incorrect WAR and WAW not possible in our 5 stage pipeline However TA test code checks for these and every semester a few WAR WAWs are found Why CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 12 LW and Hazards No load delay slot CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 13 Questions about LW and forwarding OR R3 R3 R2 LW R1 128 R29 ADDIU R1 R1 24 Do we need to stall ID Decode EX IR WB MEM IR IR IR WE MemToReg From WB Mux Logic op 32 A 32 A L U 32 Y wd R Addr RegFile rs1 rd1 rs2 ws Data Memory Dout Din WE M rd2 MemToReg M WE Ext CS 152 L9 Pipelining III B UC Regents Fall 2006 UCB 14 Questions about LW and forwarding LW R1 128 R29 OR R1 R3 R1 ADDIU R1 R1 24 Do we need to stall ID Decode EX IR WB MEM IR IR IR WE MemToReg From WB Mux Logic op 32 A 32 A L U 32 Y wd R Addr RegFile rs1 rd1 rs2 ws Data Memory Dout Din WE M rd2 MemToReg M WE Ext CS 152 L9 Pipelining III B UC Regents Fall 2006 UCB 15 Resolving a RAW hazard by stalling Stage 1 Stage 2 Instr Fetch Decode Reg Fetch Sample program ADD R4 R3 R2 OR R5 R4 R2 IR 0x4 PC D Instr Mem Q Data Freeze PC and IR until stall is over CS 152 L9 Pipelining III ADD R4 R3 R2 OR R5 R4 R2 Keep executing OR instruction until R4 is ready Until then send NOPS to IR 2 3 IR ws rd2 A New datapath hardware M 1 Mux into IR 2 3 to feed in NOP B 2 Write enable on PC and IR 1 2 WE Ext IR Let ADD proceed to WB stage so that R4 is written to regfile RegFile rs1 rd1 rs2 wd Addr Stage 3 UC Regents Fall 2006 UCB 16 Udam s Group Spr 05 Members Michael Bryant Udam Daniel 17 Problem 5 Stalling Logic was incorrect Solution Break up signal into sub wires to reduce confusion and facilitate debugging 18 Problems Don t fall into trap of using one giant module Makes it really hard to find problems Too many things are happening at the same time To solve this break things apart into submodules and use layers of abstraction 19 Stalling problems SYNCMEISTER Group FALL 05 Make sure control signals are synched with corresponding data Sometimes control signals must be delayed Take extra precautions so that stale data is not reintroduced into your processor pipeline CS 152 L11 VLSI UC Regents Fall 2005 UCB 20 Synchronous memory makes it harder CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 21 Synchronous Memory Reads Lab 3 Synchronous Memory Lab 2 Asynchronous Memory 32 32 Data Memory Addr 32 Dout CS 152 L9 Pipelining III UC Regents Fall 2006 UCB 22 Fall 05 The FOur Bytes Problems The Next PC Calculation Have to use this when start using synchronous memory Very hard to get right when dealing with stalls Try to get an understanding of the dynamics of this early on …
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