CS 152 Computer Architecture and Engineering Lecture 3 Single Cycle Wrap Up 2005 9 6 John Lazzaro www cs berkeley edu lazzaro TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Last Time Goal 1 an R format CPU Syntax ADD 8 9 10 opcode Sample ADD 8 SUB 4 AND 9 rs program 9 10 8 3 8 4 How registers get their initial values are not of concern to us right now CS 152 L3 Single Cycle Wrap up rt Semantics 8 9 10 rd shamt funct No branches or jumps machine only runs straight line code No loads or stores machine has no use for data memory only instruction memory UC Regents Fall 2005 UCB Last Time An R format CPU design Decode fields to get ADD 8 9 10 opcode rs rt rd shamt funct Logic op 5 5 5 32 RegFile rs1 rd1 rs2 32 ws 32 wd 32 CS 152 L3 Single Cycle Wrap up rd2 32 A L U 32 WE UC Regents Fall 2005 UCB Reminder How data flows after posedge Instr Mem PC D Q Addr Data 0x4 Logic op 5 5 5 32 RegFile rs1 rd1 rs2 32 ws 32 wd 32 CS 152 L3 Single Cycle Wrap up rd2 32 A L U 32 WE UC Regents Fall 2005 UCB Next posedge Update state and repeat PC 5 5 5 D Q RegFile rs1 rd1 rs2 32 ws 32 wd 32 CS 152 L3 Single Cycle Wrap up rd2 WE UC Regents Fall 2005 UCB Today s Lecture Single Cycle Wrap up Design stand alone machines for other major classes of instructions immediate ALU branches load store Learn how to efficiently merge single function machines to make one general purpose machine Implementing control structures for the single cycle datapath And also Design Notebook CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Goal 2 add I format ALU instructions Syntax ORI 8 9 64 Semantics 8 9 64 In this example 9 is rs and 8 is rt 16 bit immediate extended to 32 bits Zero extend 0x8000 0x00008000 Sign extend 0x8000 0xFFFF8000 Some MIPS instructions zero extend immediate field other instructions CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Computing engine of the I format CPU Decode fields to get ORI 8 9 64 Logic op 5 5 5 32 RegFile rs1 rd1 rs2 32 ws 32 wd 32 rd2 Ext 32 A L U 32 WE In a Verilog implementation what should we do with rs2 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Merging data paths Add muxes How many R format I format Where CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB The merged data path opcode rs rt rd shamt funct ALUctr op 5 5 5 32 ws 32 wd RegDest 32 RegFile rs1 rd1 rs2 32 rd2 WE 32 Ext ExtOp CS 152 L3 Single Cycle Wrap up 32 A L U ALUsrc UC Regents Fall 2005 UCB Administrivia Upcoming deadlines Tonight Lab 1 final report due 11 59 PM Or email to via the submit program lazzaro e design ecs Thursday Lab 2 preliminary document due to TAs via email 11 59 PM Friday Design Document Review in section 125 Cory For non 150s 150 Lab Lecture 2 3 PM 125 Cory Monday Lab 2 final design document due to TAs via email 11 59 PM CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Memory Instructions CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Loads Stores and Data Memory Syntax LW 1 32 2 Syntax SW 3 12 4 Action 1 M 2 32 Action M 4 12 3 32 Zero extend or sign extend immediate field Reads are combinational Data Memory Addr Dout Din 32 WE 32 Put a stable address on Addr a short time later Dout is ready Writes are clocked If WE is high memory Addr captures Din on positive edge of clock Note Not a realistic main memory CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Adding data memory to the data path 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 rd2 wd RegDest WE 32 RegWr ALUctr Ext ExtOp MemToReg ALUsrc MemWr Syntax LW 1 32 2 Syntax SW 3 12 4 Action 1 M 2 32 Action M 4 12 3 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Branch Instructions CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Conditional Branches in MIPS Syntax BEQ 1 2 12 Action If 1 2 PC PC 4 Action If 1 2 PC PC 4 48 Immediate field codes words Why is this notencoding bytes a good idea Zero extend or sign extend immediate field CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Adding branch testing to the data path 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 rd2 wd RegDest WE 32 RegWr ALUctr Ext ExtOp MemToReg ALUsrc MemWr Equal wire into control Syntax BEQ 1 2 12 Action If 1 2 PC PC 4 Action If 1 2 PC PC 4 48 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Recall Straight line Instruction Fetch Instr Mem Data 32 Addr Fetching straight line MIPS instructions requires a machine that generates this timing diagram 32 CLK Addr PC Data PC 4 IMem PC IMem PC 4 PC 8 IMem PC 8 PC Program Counter points to next instruction CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Recall Straight line Instruction Fetch do we add this behavio Syntax BEQ 1 2 How 12 Action If 1 2 PC PC 4 Action If 1 2 PC PC 4 48 32 PC 32 D 32 Q 32 Instr Mem 32 Addr Data 32 0x4 Clk CLK Addr Data PC CS 152 L3 Single Cycle Wrap up PC 4 IMem PC IMem PC 4 PC 8 IMem PC 8 UC Regents Fall 2005 UCB Design Instruction Fetch with Branch Syntax BEQ 1 2 12 Action If 1 2 PC PC 4 Action If 1 2 PC PC 4 48 32 PC 32 D 0x4 32 Q 32 Instr Mem 32 Addr Data 32 32 PCSrc Ex te nd Clk 32 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Single Cycle Control CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB What is single cycle control Instr Mem Addr Combinational Logic Only Gates No Flip Flops Equal Data 32 Just specify logic functions RegDest RegWr 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 rd2 wd RegDest ExtOp WE 32 RegWr CS 152 L3 Single Cycle Wrap up ALUsrc MemWr PCSrc MemToReg ALUctr Equal Ext ExtOp MemToReg ALUsrc MemWr UC Regents Fall 2005 UCB Two goals when specifying control logic Bug free One 0 that should be a 1 in the control logic function breaks contract with the …
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