CS 152 Computer Architecture and Engineering Lecture 10 Midterm I Review Session 2005 9 29 John Lazzaro www cs berkeley edu lazzaro TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Today Midterm I Review Session A tour of the midterm problems The 8 problems we expect to be on the test 2 reserve problems that may appear on the test if we find a lastminute problem bug Study tips test ground rules All questions answered almost CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Part I Single Cycle 20 40 of total points tentative CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB New Component Register for PC Built out of an array of flip flops Din0 D Q Dout0 Din1 D Q Dout1 Din2 D Q Dout2 PC 32 Din Dout Clk 32 In later examples we will add an enable input clock edge updates state only if enable is high CS 152 L10 Midterm I Review clk UC Regents Fall 2005 UCB Register File Schematic Symbol Why do we need WE If we had a register file w o WE how could we work around it 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 wd 32 CS 152 L10 Midterm I Review rd2 WE UC Regents Fall 2005 UCB Register files From the top down clk sel ws 5 Why is R0 special R0 The constant D D E WE M U X D En En R1 R2 0 Q two read ports Q Q D wd En R31 Q Even more interesting from CS 152 L10 Midterm I Review sel rs1 5 32 M U X 32 rd1 32 sel rs2 5 32 M U X 32 rd2 32 UC Regents Fall 2005 UCB Q1 Register File Design Given a spec for a register file do a logic design that meets spec The spec has unique features not present in a standard register file Things to review Register file design shown in Lecture 1 2 and the book If you are very shaky on logic you may wish to read book Appendix B CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Goal 1 An R format single cycle CPU Syntax ADD 8 9 10 Semantics 8 9 10 What do we do with these Instruction Fetch Fetch next inst from memory 012A4020 Instruction Decode opcode rs rt rd shamt funct Decode fields to get ADD 8 9 10 Operand Fetch Execute Result Store Next Instruction Retrieve register values 9 10 Add 9 to 10 Place this sum in 8 Prepare to fetch instruction that follows the ADD in the program CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Memory Instructions LW 1 32 2 Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch the load inst from memory opcode rs rt offset IFormat Decode fields to get LW 1 32 2 Retrieve register value 2 Compute memory address 32 2 Load memory address contents into 1 Prepare to fetch instr that follows the LW in the program Depending on load semantics new 1 is visible to that instr or not until the following instr delayed loads CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Branch Instructions BEQ 1 2 25 Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch branch inst from memory opcode rs rt offset IFormat Decode fields to get BEQ 1 2 25 Retrieve register values 1 2 Compute if we take branch 1 2 ALWAYS prepare to fetch instr that follows the BEQ in the program delayed branch IF we take branch the instr we fetch AFTER that instruction is PC 4 100 CS 152 L10 Midterm I Review PC Program UC Regents Fall 2005 UCB The merged data path R format imm opcode rs rt rd shamt funct ALUctr op 5 5 5 32 ws 32 wd RegDest 32 RegFile rs1 rd1 rs2 32 rd2 WE 32 Ext ExtOp CS 152 L10 Midterm I Review 32 A L U ALUsrc UC Regents Fall 2005 UCB Adding data memory to the data path 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 rd2 wd RegDest WE 32 RegWr ALUctr Ext ExtOp MemToReg ALUsrc MemWr Syntax LW 1 32 2 Syntax SW 3 12 4 Action 1 M 2 32 Action M 4 12 3 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Design Instruction Fetch with Branch Syntax BEQ 1 2 12 Action If 1 2 PC PC 4 Action If 1 2 PC PC 4 48 32 PC 32 D 0x4 32 Q 32 Instr Mem 32 Addr Data 32 32 PCSrc Ex te nd Clk 32 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2005 UCB Q2 Single Cycle CPU Design We show a single cycle CPU design slightly modified from class We propose 3 new MIPS instructions Each one is tricky in its own way Is it possible to implement the instruction on the datapath If so you design the controller If not you redesign the datapath to run the instruction Things to review Single cycle lectures readings for the lectures CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Conclusions The Architect s Contract To the program it appears that instructions execute in the correct order defined by the ISA As each instruction completes the machine state regs mem appears to the program to obey the ISA What the machine actually does is up to the hardware designers as long as the contract is kept The primary challenge of 152 CPU CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Q3 Single Cycle CPU Design We show a single cycle CPU design slightly modified from class We propose a change in the programmer s contract for the MIPS ISA You must redesign the singe cycle design to support the ISA change given a set of design constraints Things to review Single cycle lectures readings for the lectures CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Part II Energy 5 20 of total points tentative CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB 1 Joule of energy is dissipated by a 1 Amp current flowing through Also for 1 Watt for 1 a 1 Ohm resistor 1 second second 1 Watt 1 Amp flowing through 1 Ohm Energy and Performance 1 Joule 0 24 calories 1 calorie raises 1 gram of water 1 Snickers bar 273 000 calories Sad fact computers turn electrical energy into heat Computation is a byproduct Air or water carries heat away or chip melts CS 152 L10 Midterm I Review UC Regents Fall 2005 UCB Switching Energy Fundamental Physics Every logic transition dissipates energy V dd V dd C E0 2 1 C 2 E1 2 1 C 2 V V dd dd How can 1 0 Strong result Independent of technology we limit switchin State of the art CPUs 90 nm g Switching energy is 70 of total energy energy …
View Full Document
Unlocking...