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Berkeley COMPSCI 152 - Lecture 4 - Pipelining

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CS 152 Computer Architecture andEngineering Lecture 4 - PipeliningKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.be rkeley.edu /~krstehttp://inst.eecs.b erkeley.ed u/~cs1522/3/2009 CS152-Spring!092Last time in Lecture 3• Microcoding became less attractive as gap betweenRAM and ROM speeds reduced• Complex instruction sets difficult to pipeline, sodifficult to increase performance as gate count grew• Iron-law explains architecture design space– Trade instructions/program, cycles/instruction, and time/cycle• Load-Store RISC ISAs designed for efficientpipelined implementations– Very similar to vertical microcode– Inspired by earlier Cray machines2/3/2009 CS152-Spring!093“Iron Law” of Processor Performance Time = Instructions Cycles Time Program Program * Instruction * Cycle– Instructions per program depends on source code,compiler technology, and ISA– Cycles per instructions (CPI) depends upon theISA and the microarchitecture– Time per cycle depends upon themicroarchitecture and the base technologyshort1Pipelinedlong1Single-cycle unpipelinedshort>1Microcodedcycle timeCPIMicroarchitectureThis lecture2/3/2009 CS152-Spring!094An Ideal Pipeline• All objects go through the same stages• No sharing of resources between any two stages• Propagation delay through all pipeline stages is equal• The scheduling of an object entering the pipeline is not affected by the objects in other stagesstage1stage2stage3stage4These conditions generally hold for industrialassembly lines.But can an instruction pipeline satisfy the lastcondition?2/3/2009 CS152-Spring!095Pipelined MIPSTo pipeline MIPS:• First build MIPS without pipelining withCPI=1• Next, add pipeline registers to reducecycle time while maintaining CPI=12/3/2009 CS152-Spring!096Pipelined DatapathClock period can be reduced by dividing the execution of aninstruction into multiple cyclestC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably)However, CPI will increase unless instructions are pipelinedwrite-backphasefetchphaseexecutephasedecode & Reg-fetchphasememoryphaseaddrwdatardataDataMemoryweALUImmExt0x4AddaddrrdataInst.Memoryrd1GPRsrs1rs2wswdrd2weIRPC2/3/2009 CS152-Spring!097Technology AssumptionsThus, the following timing assumption is reasonable• A small amount of very fast memory (caches) backed up by a large, slower memory• Fast ALU (at least for integers)• Multiported Register files (slower!)tIM ! tRF ! tALU ! tDM ! tRWA 5-stage pipelined Harvard architecture will be the focus of our detailed design2/3/2009 CS152-Spring!0985-Stage Pipelined Executiontime t0 t1 t2 t3 t4 t5 t6 t7 . . . .instruction1 IF1ID1EX1MA1WB1instruction2 IF2ID2EX2MA2WB2instruction3 IF3ID3EX3MA3WB3instruction4 IF4ID4EX4MA4WB4instruction5 IF5ID5EX5MA5WB5Write-Back(WB)I-Fetch(IF)Execute(EX)Decode, Reg. Fetch(ID)Memory(MA)addrwdatardataDataMemoryweALUImmExt0x4AddaddrrdataInst.Memoryrd1GPRsrs1rs2wswdrd2weIRPC2/3/2009 CS152-Spring!0995-Stage Pipelined ExecutionResource Usage Diagramtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .IF I1I2I3I4I5ID I1I2I3I4I5EX I1I2I3I4I5MA I1I2I3I4I5WB I1I2I3I4I5ResourcesWrite-Back(WB)I-Fetch(IF)Execute(EX)Decode, Reg. Fetch(ID)Memory(MA)addrwdatardataDataMemoryweALUImmExt0x4AddaddrrdataInst.Memoryrd1GPRsrs1rs2wswdrd2weIRPC2/3/2009 CS152-Spring!0910Pipelined Execution:ALU InstructionsIRIRIR31PCABYRMD1MD2addrinstInstMemory0x4AddIRImmExtALUrd1GPRsrs1rs2wswd rd2wewdataaddrwdatardataData MemoryweNot quite correct!We need an Instruction Reg (IR) for each stage2/3/2009 CS152-Spring!0911Pipelined MIPS Datapathwithout jumpsIRIRIR31PCABYRMD1MD2addrinstInstMemory0x4AddIRImmExtALUrd1GPRsrs1rs2wswd rd2weData MemorywdataaddrwdatardataweOpSelExtSel BSrcWBSrcMemWriteRegDstRegWriteF D E M WControl Points Needto Be Connected2/3/2009 CS152-Spring!0912How Instructions can Interact witheach other in a pipeline• An instruction in the pipeline may need aresource being used by another instructionin the pipeline ! structural hazard• An instruction may depend on somethingproduced by an earlier instruction– Dependence may be for a data value! data hazard– Dependence may be for the next instruction’saddress! control hazard (branches, exceptions)2/3/2009 CS152-Spring!0913Data Hazards...r1 " r0 + 10r4 " r1 + 17...r1 is stale. Oops!r1 " …r4 " r1 …IRIRIR31PCABYRMD1MD2addrinstInstMemory0x4AddIRImmExtALUrd1GPRsrs1rs2wswd rd2wewdataaddrwdatardataData Memorywe2/3/2009 CS152-Spring!0914CS152 Administrivia• PS 1 due Tuesday Feb 10 in class• Section covering PS 1 on Wednesday Feb 11– Room/time TBD• First Quiz on Thursday Feb 12– In class, closed-book, no computers or calculators– Covers lectures 1-5 (this week’s lectures)• Lecture 7, Tuesday Feb 17 in 320 Soda• Lecture 8, Thursday Feb 19 back in 306 Soda• See website for full schedule2/3/2009 CS152-Spring!0915Resolving Data Hazards (1)Strategy 1:Wait for the result to be available by freezingearlier pipeline stages ! interlocks2/3/2009 CS152-Spring!0916Feedback to Resolve Hazards• Later stages provide dependence information to earlier stageswhich can stall (or kill) instructionsFB1stage1stage2stage3stage4FB2FB3FB4• Controlling a pipeline in this manner works providedthe instruction at stage i+1 can complete withoutany interference from instructions in stages 1 to i (otherwise deadlocks may occur)2/3/2009 CS152-Spring!0917IRIRIR31PCABYRMD1MD2addrinstInstMemory0x4AddIRImmExtALUrd1GPRsrs1rs2wswdrd2wewdataaddrwdatardataData MemorywenopInterlocks to resolve Data Hazards...r1 " r0 + 10r4 " r1 + 17...Stall Condition2/3/2009 CS152-Spring!0918stalled stagestimet0 t1 t2 t3 t4 t5 t6 t7 . . . .IF I1I2I3I3I3I3I4I5ID I1I2I2I2I2I3I4I5EX I1nop nop nop I2I3I4I5MA I1nop nop nop I2I3I4I5WB I1nop nop nop I2I3I4I5Stalled Stages and Pipeline Bubblestimet0 t1 t2 t3 t4 t5 t6 t7 . . . .(I1) r1 " (r0) + 10 IF1ID1EX1MA1WB1(I2) r4 " (r1) + 17 IF2ID2ID2ID2ID2EX2MA2WB2(I3) IF3IF3IF3IF3ID3EX3MA3WB3(I4) IF4ID4EX4MA4WB4(I5) IF5ID5EX5MA5WB5Resource Usagenop ! pipeline bubble2/3/2009 CS152-Spring!0919IRIRIR31PCABYRMD1MD2addrinstInstMemory0x4AddIRImmExtALUrd1GPRsrs1rs2wswdrd2wewdataaddrwdatardataData MemorywenopInterlock Control LogicCompare the source registers of the instruction in the decodestage with the destination register of the uncommittedinstructions.stallCstallwsrsrt?2/3/2009 CS152-Spring!0920CdestInterlock Control Logicignoring jumps &


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Berkeley COMPSCI 152 - Lecture 4 - Pipelining

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