CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller DesignOverview of ControlRecap: “Macroinstruction” InterpretationThe Big Picture: Where are We Now?Recap: Horizontal vs. Vertical MicroprogrammingRecap: Designing a Microinstruction SetAlternative datapath (book): Multiple Cycle DatapathFinite State Machine (FSM) Spec1&2) Start with list of control signals, grouped into fieldsStart with list of control signals, cont’d3) Microinstruction Format: unencoded vs. encoded fields4) Legend of Fields and Symbolic NamesMicroprogram it yourself!Slide 14AdministriviaMidterm I distributionMultiplierSingle Bit Booth MultiplierDouble Bit Booth MultiplierAdministrivia: Courses to consider during TelebearsLab4: start using test benchesAn Alternative MultiCycle DataPathWhat about a 2-Bus Microarchitecture (datapath)?LoadLegacy Software and MicroprogrammingMicroprogramming Pros and ConsExceptionsTwo Types of ExceptionsMIPS convention:What happens to Instruction with Exception?Precise InterruptsBig Picture: user / system modesAddressing the Exception HandlerSaving StateAdditions to MIPS ISA to support Exceptions?Recap: Details of Status registerRecap: Details of Cause registerHow Control Detects Exceptions in our FSDHow add Exceptions for Overflow and Unimplmented?Modification to the Control SpecificationPipelining is Natural!Sequential LaundryPipelined Laundry: Start work ASAPPipelining LessonsPipelined ExecutionSingle Cycle, Multiple Cycle, vs. PipelineWhy Pipeline?Why Pipeline? Because the resources are there!Can pipelining get us into trouble?Summary 1/3Summary 2/3Summary: Microprogramming one inspiration for RISC3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.1CS 152 Computer Architecture and EngineeringLecture 11Multicycle Controller Design Mar 8, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.2Overview of Control°Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.Initial Representation Finite State Diagram MicroprogramSequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth TablesImplementation PLA ROM Technique“hardwired control” “microprogrammed control”3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.3Recap: “Macroinstruction” InterpretationMainMemoryexecutionunitcontrolmemoryCPUADDSUBANDDATA...User program plus Datathis can change!AND microsequencee.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s)one of these ismapped into oneof these3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.4The Big Picture: Where are We Now? °The Five Classic Components of a Computer°Today’s Topics: •Microprogramed control•Administrivia; Courses•Microprogram it yourself•Exceptions•Intro to Pipelining (if time permits)ControlDatapathMemoryProcessorInputOutput3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.5Recap: Horizontal vs. Vertical MicroprogrammingNOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperationsMost microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal+ more control over the potential parallelism of operations in the datapath- uses up lots of control storeVertical+ easier to program, not very different from programming a RISC machine in assembly language- extra level of decoding may slow the machine down3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.6Recap: Designing a Microinstruction Set1) Start with list of control signals2) Group signals together that make sense (vs. random): called “fields”3) Places fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals•Use computers to design computers5) To minimize the width, encode operations that will never be used at the same time3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.7Alternative datapath (book): Multiple Cycle Datapath°Miminizes Hardware: 1 memory, 1 adderIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCond PCSrc32IorDMem Data RegALU OutBA3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.8Finite State Machine (FSM) SpecIR <= MEM[PC]PC <= PC + 4R-typeALUout <= A fun BR[rd] <= ALUoutALUout <= A or ZXR[rt] <= ALUoutORiALUout <= A + SXR[rt] <= MM <= MEM[ALUout]LWALUout <= A + SXMEM[ALUout] <= BSW“instruction fetch”“decode”ExecuteMemoryWrite-back00000001010001010110011110001001101010111100BEQ00100011If A = B then PC <= ALUoutALUout <= PC +SXQ: How improveto do something instate 0001?3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.91&2) Start with list of control signals, grouped into fieldsSignal name Effect when deasserted Effect when assertedALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRead None Memory at address is read, MDR <= Mem[addr]MemWrite None Memory at address is written IorD Memory address = PC Memory address = SIRWrite None IR <= MemoryPCWrite None PC <= PCSourcePCWriteCond None IF ALUzero then PC <= PCSourcePCSource PCSource = ALU PCSource = ALUout Single Bit ControlSignal name Value Effect ALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code11 ALU does logical OR ALUSelB 000 2nd ALU input = Reg[rt] 001 2nd ALU input = 4 010 2nd ALU input = sign extended IR[15-0] 011 2nd ALU input = sign extended, shift left 2 IR[15-0]100 2nd ALU input = zero extended IR[15-0] Multiple Bit Control3/8/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec11.10Start with list of control signals, cont’d° For next state function (next
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