CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design Mar 8 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 3 8 99 UCB Spring 1999 CS152 Kubiatowicz Overview of Control Control may be designed using one of several initial representations The choice of sequence control and how logic is represented can then be determined independently the control can then be implemented with one of several methods using a structured logic technique Initial Representation Sequencing Control Logic Representation Implementation Technique 3 8 99 Finite State Diagram Microprogram Explicit Next State Microprogram counter Function Dispatch ROMs Logic Equations PLA hardwired control UCB Spring 1999 Truth Tables ROM microprogrammed control CS152 Kubiatowicz Recap Macroinstruction Interpretation Main Memory ADD SUB AND DATA execution unit CPU User program plus Data this can change one of these is mapped into one of these AND microsequence control memory e g Fetch Calc Operand Addr Fetch Operand s Calculate Save Answer s 3 8 99 UCB Spring 1999 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topics Microprogramed control Administrivia Courses Microprogram it yourself Exceptions 3 8 99 Intro to Pipelining if time permits UCB Spring 1999 CS152 Kubiatowicz Recap Horizontal vs Vertical Microprogramming NOTE previous organization is not TRUE horizontal microprogramming register decoders give flavor of encoded microoperations Most microprogramming based controllers vary between horizontal organization 1 control bit per control point vertical organization fields encoded in the control memory and must be decoded to control something Horizontal Vertical more control over the potential parallelism of operations in the datapath easier to program not very different from programming a RISC machine in assembly language 3 8 99 uses up lots of control store extra level of decoding may slow the machine down UCB Spring 1999 CS152 Kubiatowicz Recap Designing a Microinstruction Set 1 Start with list of control signals 2 Group signals together that make sense vs random called fields 3 Places fields in some logical order e g ALU operation ALU operands first and microinstruction sequencing last 4 Create a symbolic legend for the microinstruction format showing name of field values and how they set the control signals Use computers to design computers 5 To minimize the width encode operations that will never be used at the same time 3 8 99 UCB Spring 1999 CS152 Kubiatowicz Alternative datapath book Multiple Cycle Datapath Miminizes Hardware 1 memory 1 adder PCWr 5 Rt 0 Rd Rb busA A Reg File Rw busW busB 1 1 Mux 0 Imm 16 ExtOp 4 B 2 Extend 1 32 32 0 UCB Spring 1999 Zero 32 0 1 32 32 2 3 ALU Control 32 MemtoReg 32 ALU Out 32 32 Rt Ra 1 ALU WrAdr 32 Din Dout 5 Mux Ideal Memory 1 0 Rs Mem Data Reg Mux RAdr 32 3 8 99 ALUSelA RegWr Mux 0 Instruction Reg 32 32 RegDst 32 PC 32 PCSrc Mux PCWrCond Zero IorD MemWr IRWr ALUOp ALUSelB CS152 Kubiatowicz Finite State Machine FSM Spec IR MEM PC instruction fetch PC PC 4 0000 decode Q How improve to do something in state 0001 0001 ALUout A fun B 0100 ORi ALUout A or ZX 0110 LW ALUout A SX 1000 M MEM ALUout 1001 R rd ALUout 0101 3 8 99 R rt ALUout 0111 BEQ SW ALUout A SX 1011 MEM ALUout B 1100 R rt M 1010 UCB Spring 1999 ALUout PC SX 0010 If A B then PC ALUout 0011 Memory Write back Execute R type CS152 Kubiatowicz Multiple Bit Control Single Bit Control 1 2 Start with list of control signals grouped into fields Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand PC 1st ALU operand Reg rs RegWrite None Reg is written MemtoReg Reg write data input ALU Reg write data input memory RegDst Reg dest no rt Reg dest no rd MemRead None Memory at address is read MDR Mem addr MemWrite None Memory at address is written IorD Memory address PC Memory address S IRWrite None IR Memory PCWrite None PC PCSource PCWriteCond None IF ALUzero then PC PCSource PCSource PCSource ALU PCSource ALUout Signal name Value Effect ALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code 11 ALU does logical OR ALUSelB 000 2nd ALU input Reg rt 001 2nd ALU input 4 010 2nd ALU input sign extended IR 15 0 011 2nd ALU input sign extended shift left 2 IR 15 0 100 2nd ALU input zero extended IR 15 0 3 8 99 UCB Spring 1999 CS152 Kubiatowicz Start with list of control signals cont d For next state function next microinstruction address use Sequencer based control unit from last lecture Called microPC or PC vs state register Signal Value Effect Sequen 00 Next address 0 cing 01 Next address dispatch ROM 10 Next address address 1 Could even include branch option which changes microPC by adding offset when certain control signals are true 3 8 99 UCB Spring 1999 1 Adder Address Select Logic microPC Mux 2 1 0 0 ROM Opcode CS152 Kubiatowicz 3 Microinstruction Format unencoded vs encoded fields Field Name Width Control Signals Set wide narrow ALU Control 4 2ALUOp SRC1 2 1ALUSelA SRC2 5 3ALUSelB ALU Destination 3 2RegWrite MemtoReg RegDst Memory 3MemRead MemWrite IorD 4 Memory Register 1 1IRWrite PCWrite Control 4 3PCWrite PCWriteCond PCSource Sequencing 3 2AddrCtl Total width 26 17bits 3 8 99 UCB Spring 1999 CS152 Kubiatowicz 4 Legend of Fields and Symbolic Names Field Name ALU Values for Field Add Subt Func code Or SRC1 PC rs SRC2 4 Extend Extend0 Extshft rt destination rd ALU rt ALU rt Mem Memory Read PC Read ALU Write ALU Memory register IR PC write ALU ALUoutCond Sequencing Seq Fetch Dispatch 3 8 99 Function of Field with Specific Value ALU adds ALU subtracts ALU does function code ALU does logical OR 1st ALU input PC 1st ALU input Reg rs 2nd ALU input 4 2nd ALU input sign ext IR 15 0 2nd ALU input zero ext IR 15 0 2nd ALU input sign ex sl IR 15 0 2nd ALU input Reg rt Reg rd ALUout Reg rt ALUout Reg rt Mem Read memory using PC Read memory using ALU output Write memory using ALU output IR Mem PC ALU IF ALU Zero then PC ALUout Go to sequential instruction Go to the first microinstruction Dispatch using ROM UCB Spring 1999 CS152 Kubiatowicz Microprogram it yourself Label ALU Fetch Add 3 8 99 SRC1 PC SRC2 ALU Dest 4 Memory Read PC UCB Spring 1999 Mem Reg PC Write IR ALU Sequencing Seq CS152 Kubiatowicz Microprogram it yourself Label ALU SRC1 SRC2 Fetch Add Add PC PC 4 Extshft Rtype Func rs rt Dest Memory Read PC Mem Reg PC Write
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