Recap Microprogramming CS152 Computer Architecture and Engineering Lecture 10 sequencer control datapath control Code ROM microinstruction Exceptions continued Introduction to Pipelining micro PC March 1 2004 sequencer fetch dispatch sequential John Kubiatowicz www cs berkeley edu kubitron To DataPath Microprogramming is a fundamental concept implement an instruction set by building a very simple processor and interpreting the instructions essential for very complex instructions and when few register transfers are possible overkill when ISA matches datapath 1 1 lecture slides http inst eecs berkeley edu cs152 3 1 04 Recap Microprogramming For instance rt ALU rd ALU mem ALU Decode Decode Dispatch ROM Opcode Decoders implement our code language CS152 Kubiatowicz Lec10 2 UCB Spring 2004 Recap Multicycle datapath book Microprogramming is a convenient method for implementing structured control state diagrams PCWr Random logic replaced by microPC sequencer and ROM Reg File Rw busW busB 1 2 Extend ExtOp 0 32 32 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2004 Zero 32 1 4 B 1 Mux 0 Imm 16 3 1 04 busA A Rb 32 ALU Out Rd Ra 1 ALU 5 Rt 0 Mux 32 5 32 Rt Mem Data Reg CS152 Kubiatowicz Lec10 3 WrAdr 32 Din Dout 32 5 Create a symbolic legend for the microinstruction format showing name of field values and how they set the control signals UCB Spring 2004 Ideal Memory 1 1 Start with list of control signals 2 Group signals together that make sense vs random called fields 3 Place fields in some logical order e g ALU operation ALU operands first and microinstruction sequencing last 4 To minimize the width encode operations that will never be used at the same time 3 1 04 RAdr Mux 32 0 0 Rs Mux 32 Design of a Microprogramming language ALUSelA RegWr Mux PC 32 RegDst 32 Instruction Reg Each line of ROM called a instruction contains sequencer control values for control points limited state transitions branch to zero next sequential branch to instruction address from displatch ROM PCSrc PCWrCond Zero IorD MemWr IRWr MemRd ALUOp ALUSelB CS152 Kubiatowicz Lec10 4 SRC1 SRC2 dest ination Mem ory Memreg PCwrite Seq uencing 3 1 04 PCwrite Ideal Memory 1 WrAdr 32 Din Dout 32 32 Rt Rd Seq Values for Field Function of Field with Specific Value Add ALU adds Subt ALU subtracts Func ALU does function code Or ALU does logical OR PC 1st ALU input PC rs 1st ALU input Reg rs 4 2nd ALU input 4 Extend 2nd ALU input sign ext IR 15 0 Extend0 2nd ALU input zero ext IR 15 0 Extshft 2nd ALU input sign ex sl IR 15 0 rt 2nd ALU input Reg rt rd ALU Reg rd ALUout rt ALU Reg rt ALUout rt Mem Reg rt Mem Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addr IR IR Mem PCwr PC PCSource PCSrc IF Zero then PCSource ALUout else ALU PCWrCond IF Zero then PC PCSource Seq Go to next sequential instruction CS152 Kubiatowicz UCB Spring Fetch Go to2004 the first microinstruction Lec10 7 Dispatch Dispatch using ROM SRC2 busA A Rb 5 Rt 0 Reg File Rw B 1 1 Mux 0 2 Extend 0 UCB Spring 2004 Zero 32 32 32 0 1 32 32 2 3 ALU Control 32 MemtoReg 32 1 4 busW busB ExtOp 3 1 04 Ra 5 1 ALU Out Field Name ALU SRC Dest Mem Memreg 2 RAdr 0 Rs Imm 16 Recap Group into Fields Order and Assign Names ALU SRC 1 0 32 CS152 Kubiatowicz Lec10 5 ALUSelA ALU UCB Spring 2004 32 32 SRC1 32 PC 32 PCSrc PCWrCond Destination Memory Zero MemWr IorD IRWr RegDst RegWr MemRd Mux 3 1 04 Effect ALU adds ALU subtracts ALU does function code ALU does logical OR 2nd ALU input 4 2nd ALU input Reg rt 2nd ALU input extended shift left 2 2nd ALU input extended PCWr Mux Signal name Value ALUOp 00 01 10 11 ALUSelB 00 01 10 11 PCWrite Mem Data Reg Effect when deasserted Effect when asserted 1st ALU operand PC 1st ALU operand Reg rs None Reg is written Reg write data input ALU Reg write data input memory Reg dest no rt Reg dest no rd None Memory at address is read MDR Mem addr MemWrite None Memory at address is written IorD Memory address PC Memory address S IRWrite None IR Memory PCWrite None PC PCSource PCWriteCond None IF ALUzero then PC PCSource PCSource PCSource ALU PCSource ALUout ExtOp Zero Extended Sign Extended Mux Signal name ALUSelA RegWrite MemtoReg RegDst MemRead Instruction Reg Multiple Bit Control Recap Group together related signals Mux Single Bit Control Recap Start with List of control signals ALUOp ALU ALUSelB CS152 Kubiatowicz Lec10 6 Recap Quick check what do these fieldnames mean Destination Code 00 01 10 11 Name rd ALU rt ALU rt MEM RegWrite 0 1 1 1 MemToReg X 0 0 1 Name 4 rt ExtShft Extend Extend0 ALUSelB X 00 01 10 11 11 ExtOp X X X 1 1 0 RegDest X 1 0 0 SRC2 Code 000 001 010 011 100 111 3 1 04 UCB Spring 2004 CS152 Kubiatowicz Lec10 8 Recap Finite State Machine FSM Spec IR MEM PC Recap Microprogram it yourself Addr Fetch 0000 0001 instruction fetch PC PC 4 0000 ALUout PC SX decode 0001 ORi ALUout A fun B ALUout A or ZX 0100 0110 LW ALUout A SX 1000 M MEM ALUout 1001 BEQ SW ALUout A SX 1011 If A B then PC ALUout 0010 MEM ALUout B 1100 R rd ALUout 0101 3 1 04 R rt ALUout 0111 R rt M 1010 Memory Write back Execute R type CS152 Kubiatowicz Lec10 9 UCB Spring 2004 BEQ 0010 Rtype 0100 0101 ORI 0110 0111 LW 1000 1001 1010 SW 1011 1100 PC 4 PC Extshft Read PC Subt rs rt Func rs rt Or Add IR ALU Seq Dispatch ALUoutCond rd ALU Seq Fetch rs Extend0 rt ALU Seq Fetch rs Extend Seq Seq Fetch Read ALU rt MEM Add Fetch rs Extend Seq Fetch Write ALU UCB Spring 2004 CS152 Kubiatowicz Lec10 10 Control may be designed using one of several initial representations The choice of sequence control and how logic is represented can then be determined independently the control can then be implemented with one of several methods using a structured logic technique Called microPC or PC vs state register Code Name Effect 00 fetch Next address 0 01 dispatch Next address dispatch ROM 10 seq Next address address 1 3 1 04 Add Add Review Overview of Control Sequencer based control unit from last lecture ROM Memory Mem Reg PC Write Sequencing 3 1 04 Recap Specific Sequencer from last lecture Opcode Dispatch state 000000 Rtype 0100 000100 BEQ 0010 001101 ORI 0110 100011 LW 1000 101011 SW 1011 ALU SRC1 SRC2 Dest Initial Representation Finite State Diagram Microprogram 1 Adder Address Select Logic UCB Spring 2004 microPC Mux 1 0 0 ROM Sequencing Control Explicit Next State Microprogram counter Function Dispatch ROMs 2 Logic …
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