UC Regents Fall 2004 © UCBCS 152 L21: Advanced Processors II2004-11-16 Dave Patterson(www.cs.berkeley.edu/~patterson)John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 21 – Advanced Processors IIwww-inst.eecs.berkeley.edu/~cs152/Thanks to Krste Asanovic ...1UC Regents Fall 2004 © UCBCS 152 L21: Advanced Processors IILast Time: Superpipelining & SuperscalarSecondsProgram InstructionsProgram=SecondsCycle InstructionCycles1600 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001Fig. 1. Process SEM cross section.The process was raised from [1] to limit standby power.Circuit design and architectural pipelining ensure low voltageperformance and functionality. To further limit standby currentin handheld ASSPs, a longer poly target takes advantage of theversus dependence and source-to-body bias is usedto electrically limit transistor in standby mode. All corenMOS and pMOS transistors utilize separate source and bulkconnections to support this. The process includes cobalt disili-cide gates and diffusions. Low source and drain capacitance, aswell as 3-nm gate-oxide thickness, allow high performance andlow-voltage operation.III. ARCHITECTUREThe microprocessor contains 32-kB instruction and datacaches as well as an eight-entry coalescing writeback buffer.The instruction and data cache fill buffers have two and fourentries, respectively. The data cache supports hit-under-missoperation and lines may be locked to allow SRAM-like oper-ation. Thirty-two-entry fully associative translation lookasidebuffers (TLBs) that support multiple page sizes are providedfor both caches. TLB entries may also be locked. A 128-entrybranch target buffer improves branch performance a pipelinedeeper than earlier high-performance ARM designs [2], [3].A. Pipeline OrganizationTo obtain high performance, the microprocessor core utilizesa simple scalar pipeline and a high-frequency clock. In additionto avoiding the potential power waste of a superscalar approach,functional design and validation complexity is decreased at theexpense of circuit design effort. To avoid circuit design issues,the pipeline partitioning balances the workload and ensures thatno one pipeline stage is tight. The main integer pipeline is sevenstages, memory operations follow an eight-stage pipeline, andwhen operating in thumb mode an extra pipe stage is insertedafter the last fetch stage to convert thumb instructions into ARMinstructions. Since thumb mode instructions [11] are 16 b, twoinstructions are fetched in parallel while executing thumb in-structions. A simplified diagram of the processor pipeline isFig. 2. Microprocessor pipeline organization.shown in Fig. 2, where the state boundaries are indicated bygray. Features that allow the microarchitecture to achieve highspeed are as follows.The shifter and ALU reside in separate stages. The ARM in-struction set allows a shift followed by an ALU operation in asingle instruction. Previous implementations limited frequencyby having the shift and ALU in a single stage. Splitting this op-eration reduces the critical ALU bypass path by approximately1/3. The extra pipeline hazard introduced when an instruction isimmediately followed by one requiring that the result be shiftedis infrequent.Decoupled Instruction Fetch. A two-instruction deep queue isimplemented between the second fetch and instruction decodepipe stages. This allows stalls generated later in the pipe to bedeferred by one or more cycles in the earlier pipe stages, therebyallowing instruction fetches to proceed when the pipe is stalled,and also relieves stall speed paths in the instruction fetch andbranch prediction units.Deferred register dependency stalls. While register depen-dencies are checked in the RF stage, stalls due to these hazardsare deferred until the X1 stage. All the necessary operands arethen captured from result-forwarding busses as the results arereturned to the register file.One of the major goals of the design was to minimize the en-ergy consumed to complete a given task. Conventional wisdomhas been that shorter pipelines are more efficient due to re-Q. Could adding pipeline stages reduce CPI for an application?ARM XScale8 stagesCPI ProblemPossible SolutionExtra branch delaysBranch predictionExtra load delaysOptimize codeStructural hazardsOptimize code, add hardwareA. Yes, due to these problems:2UC Regents Fall 2004 © UCBCS 152 L21: Advanced Processors IIToday: Dynamic Scheduling OverviewGoal: Enable out-of-order by breaking pipeline in two: fetch and execution.Example: IBM Power 5: The Power5 scans fetched instructions forbranches (BP stage), and if it finds a branch,predicts the branch direction using threebranch history tables shared by the twothreads. Two of the BHTs use bimodal andpath-correlated branch prediction mecha-nisms to predict branch directions.6,7Thethird BHT predicts which of these predictionmechanisms is more likely to predict the cor-rect direction.7If the fetched instructions con-tain multiple branches, the BP stage can pre-dict all the branches at the same time. Inaddition to predicting direction, the Power5also predicts the target of a taken branch inthe current cycle’s eight-instruction group. Inthe PowerPC architecture, the processor cancalculate the target of most branches from theinstruction’s address and offset value. For43MARCH–APRIL 2004MP ISS RF EA DC WB XferMP ISS RF EX WB XferMP ISS RF EX WB XferMP ISS RFXferF6Group formation andinstruction decodeInstruction fetchBranch redirectsInterrupts and flushesWBFmtD1 D2 D3 Xfer GDBPICCPD0IFBranchpipelineLoad/storepipelineFixed-pointpipelineFloating-point pipelineOut-of-order processingFigure 3. Power5 instruction pipeline (IF = instruction fetch, IC = instruction cache, BP = branch predict, D0 = decode stage0, Xfer = transfer, GD = group dispatch, MP = mapping, ISS = instruction issue, RF = register file read, EX = execute, EA =compute address, DC = data caches, F6 = six-cycle floating-point execution pipe, Fmt = data format, WB = write back, andCP = group commit).Shared by two threads Thread 0 resources Thread 1 resourcesLSU0FXU0LSU1FXU1FPU0FPU1BXUCRLDynamicinstructionselectionThreadpriorityGroup formationInstruction decodeDispatchShared-registermappersReadshared-register filesSharedissuequeuesSharedexecutionunitsAlternateBranch prediction
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