CS152 Computer Architecture and Engineering Lecture 7 Designing a Single Cycle Datapath February 18 2004 John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 2 18 03 UCB Spring 2004 CS152 Kubiatowicz Review Sequential Logic Non blocking assignments Must be careful mixing zero time blocking assignments and edge triggering Probably won t do what you expect when connecting it to other things module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q D endmodule FF Good Doesn t output until after edge Probably Not what you Expect Hold time of 5 units glitches 5 units ignored 2 19 03 module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q 5 D endmodule FF Good Outputs 5 units after edge module FF CLK Q D input D CLK output Q reg Q always posedge CLK 5 Q D endmodule FF UCB Spring 2003 CS152 Kubiatowicz Review MULTIPLY HARDWARE Version 3 32 bit Multiplicand reg 32 bit ALU 64 bit Product reg shift right 0 bit Multiplier reg Multiplican d 32 bits 32 bit ALU HI LO Shift Right Product Multiplier 64 bits 2 19 03 Control Write UCB Spring 2003 CS152 Kubiatowicz Divide can use almost same hardware From Book 32 bit Divisor reg 32 bit ALU 64 bit Remainder reg 0 bit Quotient reg Divisor 32 bits 32 bit ALU HI LO Shift Left Remainder Quotient 64 bits Control Write Multiplication and Division can use same hardware 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Review Booth s Algorithm Alternate representation end of run middle of run beginning of run 0 1 1 1 1 0 Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 1 Middle of run of 1s 0001111000 none 0 0 1 End of run of 1s 0001111000 add 1 0 0 Middle of run of 0s 0001111000 none 0 Examples 8 bits 3 11111101 00000 1 1 1 4 2 1 14 00001110 000100 1 0 16 2 23 00010111 001 1 100 1 32 16 8 1 2 19 03 UCB Spring 2003 CS152 Kubiatowicz MIPS logical instructions Instruction Example Meaning Comment and and 1 2 3 1 2 3 3 reg operands Logical AND or or 1 2 3 1 2 3 3 reg operands Logical OR xor xor 1 2 3 1 2 3 3 reg operands Logical XOR nor nor 1 2 3 1 2 3 3 reg operands Logical NOR and immediate andi 1 2 10 1 2 10 Logical AND reg constant or immediate ori 1 2 10 1 2 10 Logical OR reg constant xor immediate xori 1 2 10 1 2 10 Logical XOR reg constant shift left logical sll 1 2 10 1 2 10 Shift left by constant shift right logical srl 1 2 10 1 2 10 Shift right by constant shift right arithm sra 1 2 10 1 2 10 Shift right sign extend shift left logical sllv 1 2 3 1 2 3 Shift left by variable shift right logical srlv 1 2 3 1 2 3 Shift right by variable shift right arithm srav 1 2 3 1 2 3 Shift right arith by variable 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Shifters Two kinds logical RIGHT OR LEFT value shifted in is always 0 0 msb lsb 0 arithmetic RIGHT ONLY sign extend msb lsb 0 Note these are single bit shifts A given instruction might request 0 to 32 bits to be shifted 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Barrel Shifter Technology dependent solutions transistor per switch SR3 SR2 SR1 SR0 D3 D2 A6 D1 A5 D0 A4 2 19 03 A3 A2 A1 UCB Spring 2003 A0 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topic Design a Single Cycle Processor machine design inst set design L1 2 2 19 03 Arithmetic L4 6 technology L3 UCB Spring 2003 CS152 Kubiatowicz The Big Picture The Performance Perspective Performance of a machine is determined by CPI Instruction count Clock cycle time Clock cycles per instruction Inst Count Cycle Time Processor design datapath and control will determine Clock cycle time Clock cycles per instruction Today Single cycle processor 2 19 03 Advantage One clock cycle per instruction Disadvantage long cycle time CS152 Kubiatowicz UCB Spring 2003 How to Design a Processor step bystep 1 Analyze instruction set datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers possibly more datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic 2 19 03 UCB Spring 2003 CS152 Kubiatowicz The MIPS Instruction Formats All MIPS instructions are 32 bits long The three instruction formats 31 26 op 6 bits R type 31 I type J type 21 rs 5 bits 26 op 6 bits 31 16 rt 5 bits 21 rs 5 bits 11 rd 5 bits 6 shamt 5 bits 16 0 funct 6 bits 0 immediate rt 5 bits 16 bits 26 0 op target address 6 bits 26 bits The different fields are op operation of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value 2 19 03 target address target address of the jump instruction UCB Spring 2003 CS152 Kubiatowicz Step 1a The MIPS lite Subset for today ADD and SUB addU rd rs rt 31 op 31 21 rs 6 bits subU rd rs rt OR Immediate ori rt rs imm16 26 op rt 5 bits 26 5 bits 21 rs 6 bits 31 26 LOAD and STORE Word op lw rt rs imm16 6 bits 16 11 6 rd shamt funct 5 bits 5 bits 6 bits 16 rt 0 0 immediate 5 bits 21 rs 5 bits 5 bits 16 rt 5 bits 21 16 16 bits 0 immediate 16 bits sw rt rs imm16 31 BRANCH beq rs rt imm16 2 19 03 26 op 6 bits rs 5 bits UCB Spring 2003 rt 5 bits 0 immediate 16 bits CS152 Kubiatowicz Logical Register Transfers RTL gives the meaning of the instructions All start by fetching the instruction op rs rt rd shamt funct MEM PC op rs rt Imm16 MEM PC inst Register Transfers ADDU R rd R rs R rt PC PC 4 SUBU R rd R rs R rt PC PC 4 ORi R rt R rs zero ext Imm16 PC PC 4 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 STORE MEM R rs sign ext Imm16 R rt PC PC 4 BEQ 2 19 03 if R rs R rt then PC PC 4 sign ext Imm16 00 else PC …
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