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Berkeley COMPSCI 152 - Memory

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Slide 1Last time in Lecture 5Early Read-Only Memory TechnologiesEarly Read/Write Main Memory TechnologiesCore MemorySemiconductor MemoryOne Transistor Dynamic RAM [Dennard, IBM]Modern DRAM StructureDRAM ArchitectureDRAM OperationDouble-Data Rate (DDR2) DRAMDRAM PackagingCPU-Memory BottleneckSlide 14Physical Size Affects LatencyMemory HierarchyRelative Memory Cell SizesCS152 AdministriviaManagement of Memory HierarchyReal Memory Reference PatternsTypical Memory Reference PatternsCommon Predictable PatternsMemory Reference PatternsCachesInside a CacheCache Algorithm (Read)Placement PolicyDirect-Mapped CacheSlide 292-Way Set-Associative CacheFully Associative CacheReplacement PolicyAcknowledgementsFebruary 4, 2010 CS152, Spring 2010CS 152 Computer Architecture and Engineering Lecture 6 - MemoryKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs152February 4, 2010 CS152, Spring 20102Last time in Lecture 5•Control hazards (branches, interrupts) are most difficult to handle as they change which instruction should be executed next•Speculation commonly used to reduce effect of control hazards (predict sequential fetch, predict no exceptions)•Branch delay slots make control hazard visible to software•Precise exceptions: stop cleanly on one instruction, all previous instructions completed, no following instructions have changed architectural state•To implement precise exceptions in pipeline, shift faulting instructions down pipeline to “commit” point, where exceptions are handled in program orderFebruary 4, 2010 CS152, Spring 2010Early Read-Only Memory Technologies3Punched cards, From early 1700s through Jaquard Loom, Babbage, and then IBMPunched paper tape, instruction stream in Harvard Mk 1IBM Card Capacitor ROSIBM Balanced Capacitor ROSDiode Matrix, EDSAC-2 µcode storeFebruary 4, 2010 CS152, Spring 2010Early Read/Write Main Memory Technologies4Williams Tube, Manchester Mark 1, 1947Babbage, 1800s: Digits stored on mechanical wheelsMercury Delay Line, Univac 1, 1951Also, regenerative capacitor memory on Atanasoff-Berry computer, and rotating magnetic drum memory on IBM 650February 4, 2010 CS152, Spring 20105Core Memory•Core memory was first large scale reliable main memory–invented by Forrester in late 40s/early 50s at MIT for Whirlwind project•Bits stored as magnetization polarity on small ferrite cores threaded onto 2 dimensional grid of wires•Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads)DEC PDP-8/E Board, 4K words x 12 bits, (1968)•Robust, non-volatile storage•Used on space shuttle computers until recently•Cores threaded onto wires by hand (25 billion a year at peak production)•Core access time ~ 1msFebruary 4, 2010 CS152, Spring 20106Semiconductor Memory•Semiconductor memory began to be competitive in early 1970s–Intel formed to exploit market for semiconductor memory–Early semiconductor memory was Static RAM (SRAM). SRAM cell internals similar to a latch (cross-coupled inverters).•First commercial Dynamic RAM (DRAM) was Intel 1103–1Kbit of storage on single chip–charge on a capacitor used to hold value•Semiconductor memory quickly replaced core in ‘70sFebruary 4, 2010 CS152, Spring 20107One Transistor Dynamic RAM [Dennard, IBM]TiN top electrode (VREF)Ta2O5 dielectricW bottomelectrodepolywordlineaccess transistor1-T DRAM Cellwordbitaccess transistorStoragecapacitor (FET gate, trench, stack)VREFFebruary 4, 2010 CS152, Spring 2010Modern DRAM Structure8[Samsung, sub-70nm DRAM, 2004]February 4, 2010 CS152, Spring 20109DRAM ArchitectureRow Address DecoderCol.1Col.2MRow 1Row 2NColumn Decoder & Sense AmplifiersMNN+Mbit linesword linesMemory cell(one bit)DData• Bits stored in 2-dimensional arrays on chip• Modern chips have around 4 logical banks on each chip– each logical bank physically implemented as many smaller arraysFebruary 4, 2010 CS152, Spring 201010DRAM OperationThree steps in read/write access to a given bank•Row access (RAS)–decode row address, enable addressed row (often multiple Kb in row)–bitlines share charge with storage cell–small change in voltage detected by sense amplifiers which latch whole row of bits–sense amplifiers drive bitlines full rail to recharge storage cells•Column access (CAS)–decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package)–on read, send latched bits out to chip pins–on write, change sense amplifier latches which then charge storage cells to required value–can perform multiple column accesses on same row without another row access (burst mode)•Precharge–charges bit lines to known value, required before next row accessEach step has a latency of around 15-20ns in modern DRAMsVarious DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share same core architectureFebruary 4, 2010 CS152, Spring 201011Double-Data Rate (DDR2) DRAM[ Micron, 256Mb DDR2 SDRAM datasheet ]Row Column Precharge Row’Data200MHz Clock400Mb/s Data RateFebruary 4, 2010 CS152, Spring 201012DRAM Packaging•DIMM (Dual Inline Memory Module) contains multiple chips with clock/control/address signals connected in parallel (sometimes need buffers to drive signals to all chips)•Data pins work together to return wide word (e.g., 64-bit data bus using 16x4-bit parts)Address lines multiplexed row/column addressClock and control signalsData bus(4b,8b,16b,32b)DRAM chip~12~7February 4, 2010 CS152, Spring 201013CPU-Memory BottleneckMemoryCPUPerformance of high-speed computers is usuallylimited by memory bandwidth & latency• Latency (time for a single access)Memory access time >> Processor cycle time• Bandwidth (number of accesses per unit time)if fraction m of instructions access memory,1+m memory references / instructionÞCPI = 1 requires 1+m memory refs / cycle(assuming MIPS RISC ISA)February 4, 2010 CS152, Spring 201014Processor-DRAM Gap (latency)TimeµProc 60%/yearDRAM7%/year110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)PerformanceFour-issue 2GHz superscalar accessing 100ns DRAM could execute 800 instructions during time for one memory access!February 4, 2010 CS152, Spring 2010Physical Size Affects


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Berkeley COMPSCI 152 - Memory

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