CS152 Computer Architecture and Engineering Lecture 24 Busses continued Queueing Theory Disk IO November 28 2001 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap Making address translation practical TLB Virtual memory memory acts like a cache for the disk Page table maps virtual page numbers to physical frames Translation Look aside Buffer TLB is a cache translations virtual address Virtual Address Space Physical Memory Space page off Page Table 2 0 1 3 TLB physical address page off frame page 2 2 0 5 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap Overlapped TLB Cache Access If we do this in parallel we have to be careful however assoc lookup 32 index TLB 4K Cache 10 2 disp 00 20 page 1K 4 bytes Hit Miss FN FN Data Hit Miss What if cache size is increased to 8KB 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap A Three Bus System backside cache Processor Memory Bus Processor Backside Cache bus L2 Cache Memory Bus Adaptor Bus Adaptor Bus Adaptor I O Bus I O Bus A small number of backplane buses tap into the processor memory bus Processor memory bus is only used for processor memory traffic I O buses are connected to the backplane bus Advantage loading on the processor bus is greatly reduced 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap Main components of Intel Chipset Pentium II III Northbridge Handles memory Graphics Southbridge I O PCI bus Disk controllers USB controlers Audio Serial I O Interrupt controller Timers 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap Synchronous and Asynchronous Bus Synchronous Bus Includes a clock in the control lines A fixed protocol relative to the clock Advantage little logic and very fast Disadvantages Every device on the bus must run at the same clock rate To avoid clock skew they cannot be long if they are fast Asynchronous Bus It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Multiple Potential Bus Masters the Need for Arbitration Bus arbitration scheme A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus Bus arbitration schemes usually try to balance two factors Bus priority the highest priority device should be serviced first Fairness Even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four broad classes Daisy chain arbitration Centralized parallel arbitration Distributed arbitration by self selection each device wanting the bus places a code indicating its identity on the bus Distributed arbitration by collision detection Each device just goes for it Problems found after the fact 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Arbitration Obtaining Access to the Bus Control Master initiates requests Bus Master Data can go either way Bus Slave One of the most important issues in bus design How is the bus reserved by a device that wishes to use it Chaos is avoided by a master slave arrangement Only the bus master can control access to the bus It initiates and controls all bus requests A slave responds to read and write requests The simplest system Processor is the only bus master All bus requests must be controlled by the processor Major drawback the processor is involved in every transaction 11 28 01 UCB Fall 2001 CS152 Kubiatowicz The Daisy Chain Bus Arbitrations Scheme Device 1 Highest Priority Grant Device N Lowest Priority Device 2 Grant Grant Release Bus Arbiter Request wired OR Advantage simple Disadvantages Cannot assure fairness A low priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Centralized Parallel Arbitration Device 1 Grant Device 2 Device N Req Bus Arbiter Used in essentially all processor memory busses and in high speed I O busses 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Increasing the Bus Bandwidth Separate versus multiplexed address and data lines Address and data can be transmitted in one bus cycle if separate address and data lines are available Cost a more bus lines b increased complexity Data bus width By increasing the width of the data bus transfers of multiple words require fewer bus cycles Example SPARCstation 20 s memory bus is 128 bit wide Cost more bus lines Block transfers Allow the bus to transfer multiple words in back to back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost a increased complexity b decreased response time for request 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Increasing Transaction Rate on Multimaster Bus Overlapped arbitration perform arbitration for next transaction during current transaction Bus parking master can holds onto bus and performs multiple transactions as long as no other master makes request Overlapped address data phases prev slide requires one of the above techniques Split phase or packet switched bus completely separate address and data phases arbitrate separately for each address phase yield a tag which is matched with data phase All of the above in most modern buses 11 28 01 UCB Fall 2001 CS152 Kubiatowicz What is DMA Direct Memory Access Typical I O devices must transfer large amounts of data to memory of processor Disk must transfer complete block Large packets from network Regions of frame buffer DMA gives external device ability to access memory directly much lower overhead than having processor request one word at a time Issue Cache coherence What if I O devices write data that is currently in processor Cache The processor may never see new data Solutions Flush cache on every I O operation expensive Have hardware invalidate cache lines remember Coherence cache misses 11 28 01 UCB Fall 2001 CS152 Kubiatowicz Administrivia Get going on Lab 7 Status update due Monday in Section Talk with Tas about the state of your project Midterm II on Friday 5 30 8 30 in 277 Cory Pizza afterwards Topics Pipelining Caches Memory systems Buses and I O Disk equation Power Queueing theory Can bring 1 page of notes Handwitten double sided CLOSED BOOK 11 28 01 UCB Fall 2001 CS152 Kubiatowicz I O System Design Issues Performance Expandability Resilience in the face of failure
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