2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.1Feb 3, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/CS152Computer Architecture and EngineeringLecture 4Cost and Design2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.2YearPerformance0.111010010001965 1970 1975 1980 1985 1990 1995 2000MicroprocessorsMinicomputersMainframesSupercomputersReview: Performance and Technology Trends° Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year• Feature Size: shrinks 10% / yr. => Switching speed improves 1.2 / yr.• Density: improves 1.2x / yr.• Die Area: 1.2x / yr.° RISC lesson is to keep the ISA as simple as possible:• Shorter design cycle => fully exploit the advancing technology (~3yr)• Advanced branch prediction and pipeline techniques• Bigger and more sophisticated on-chip caches2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.3Review: Technology, Logic Design and Delay° CMOS Technology Trends• Complementary: PMOS and NMOS transistors• CMOS inverter and CMOS logic gates° Delay Modeling and Gate Characterization• Delay = Internal Delay + (Load Dependent Delay x Output Load)° Clocking Methodology and Timing Considerations• Simplest clocking methodology- All storage elements use the SAME clock edge• Cycle Time = CLK-to-Q + Longest Delay Path + Setup + ClockSkew• (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.4Overview: Cost and Design° Review from Last Lecture (2 minutes)° Cost and Price (18)° Administrative Matters (3 minutes)° Design process (27 minutes)° Break (5 minutes)° More Design process (15 minutes)° Online notebook (10 minutes)2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.5Defects_per_unit_area * Die_Area αα}Integrated Circuit CostsDie Cost is goes roughly with the cube of the area.{ 1+Die cost = Wafer cost Dies per Wafer * Die yieldDies per wafer = π * ( Wafer_diam / 2)2 – π * Wafer_diam – Test dies ≈ Wafer Area Die Area √ 2 * Die Area Die AreaDie Yield = Wafer yield2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.6Die YieldRaw Dice Per Waferwafer diameter die area (mm2)100144 196 256 324 4006”/15cm 139 90 62 44 32 238”/20cm 265 177 124 90 68 5210”/25cm 431 290 206 153 116 90die yield 23% 19% 16% 12% 11% 10%typical CMOS process: α =2, wafer yield=90%, defect density=2/cm2, 4 test sites/waferGood Dice Per Wafer (Before Testing!)6”/15cm 31 16 9 5 3 28”/20cm 59 32 19 11 7510”/25cm 96 53 32 20 13 9typical cost of an 8”, 4 metal layers, 0.5um CMOS wafer: ~$20002/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.7Real World ExamplesChip Metal Line Wafer Defect Area Dies/ Yield Die Costlayers width cost /cm2mm2wafer386DX 2 0.90 $900 1.0 43 360 71% $4486DX2 3 0.80 $1200 1.0 81 181 54% $12PowerPC 601 4 0.80 $1700 1.3 121 115 28% $53HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149SuperSPARC 3 0.70 $1700 1.6 256 48 13% $272Pentium 3 0.80 $1500 1.5 296 40 9% $417From "Estimating IC Manufacturing Costs,” by Linley Gwennap, Microprocessor Report,August 2, 1993, p. 152/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.8IC cost = Die cost + Testing cost + Packaging cost Final test yieldPackaging Cost: depends on pins, heat dissipationOther CostsChip Die Package Test & Totalcost pins type cost Assembly386DX $4 132 QFP $1 $4 $9486DX2 $12 168 PGA $11 $12 $35PowerPC 601 $53 304 QFP $3 $21 $77HP PA 7100 $73 504 PGA $35 $16 $124DEC Alpha $149 431 PGA $30 $23 $202SuperSPARC $272 293 PGA $20 $34 $326Pentium $417 273 PGA $19 $37 $4732/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.9System Cost: -1995-96 Workstation System Subsystem % of total costCabinet Sheet metal, plastic 1%Power supply, fans 2%Cables, nuts, bolts 1%(Subtotal) (4%)Motherboard Processor 6%DRAM (64MB) 36%Video system 14%I/O system 3%Printed Circuit board 1%(Subtotal) (60%)I/O Devices Keyboard, mouse 1%Monitor 22%Hard disk (1 GB) 7%Tape drive (DAT) 6%(Subtotal) (36%)2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.10ComponentCostcomponentcostDirect Costscomponentcostdirect costsGross Margincomponentcostdirect costsgross marginAverageDiscountlist priceavg. selling priceInput: chips, displays, ...Making it:labor, scrap,returns, ...Overhead:R&D, rent,marketing,profits, ...Commision:channelprofit, volumediscounts,+33%+25–100%+50–80%(25–31%)(33–45%)(8–10%)(33–14%)(WS–PC)Q: What % of company incomeon Research and Development (R&D)?Cost vs. Price2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.11Cost Summary° Integrated circuits driving computer industry° Die costs goes up with the cube of die area° Economics ($$$) is the ultimate driver forperformance!2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.12Administrative Matters° Review complete: did ok on prob 1 & 4.Problems 2 and 3 more challengingMake sure you look at solutions!° Read Chapter 4: ALU, Multiply, Divide, FP Mult° Dollars for bugs! First to report bug gets $1 check• Send 1 bug/ email to [email protected]• Include page number, orginal text, why bug, fixed text2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.13The Design Process"To Design Is To Represent"Design activity yields description/representation of an object-- Traditional craftsman does not distinguish between the conceptualization and the artifact-- Separation comes about because of complexity-- The concept is captured in one or more representation languages-- This process IS designDesign Begins With Requirements-- Functional Capabilities: what it will do-- Performance Characteristics: Speed, Power, Area, Cost, . . .2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.14Design Process (cont.)Design Finishes As Assembly-- Design understood in terms of components and how they have been assembled-- Top Down decomposition of complex functions (behaviors) into more primitive functions-- bottom-up composition of primitive building blocks into more complex assembliesCPUDatapath ControlALU Regs ShifterNandGateDesign is a "creative process," not a simple method2/3/99 ©UCB Spring 1999CS152 / KubiatowiczLec4.15Design RefinementInformal System RequirementInitial SpecificationIntermediate SpecificationFinal Architectural DescriptionIntermediate Specification of ImplementationFinal Internal SpecificationPhysical
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