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Berkeley COMPSCI 152 - CS 152 Final Project

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Table Of Contents0. Abstract1. Division of Labor2. Detailed Strategy2.2 Stage Summary2.3 Stage Details2.4 Forwarding Paths3. Testing3.1 General testing.3.2 Victim Cache test.3.3 Branch Predictor.3.4 (Un)Signed Multiply/Divide.4. Results4.1 Write-Back & Victim Cache:4.2 Branch Predictor4.3 Deep Pipelining5. Conclusion6. Appendix I (Notebooks)7. Appendix II (Schematics)8. Appendix III (Verilog Files)9. Appendix IV (Test Files)10. Appendix V (Timing)============================================================Timing constraint: Default period analysis for net "processo7782172 items analyzed, 0 timing errors detected. (0 setup eMinimum period is 36.799ns.------------------------------------------------------------Delay: 36.799ns (data path - clock path skeSource: DP/S1_dff/Q[7] (FF)Destination: CACHE_UNIT/dc/dtf/B5.A (RAM)Data Path Delay: 36.762ns (Levels of Logic = 12)Clock Path Skew: -0.037nsSource Clock: processor_clock risingDestination Clock: processor_clock risingClock Uncertainty: 0.000nsData Path: DP/S1_dff/Q[7] to CACHE_UNIT/dc/dtf/B5.ADelay type Delay(ns) Logical Resource(s)---------------------------- -------------------Tcko 0.992 DP/S1_dff/Q[7]net (fanout=50) 2.878 S1[7]Topcyg 1.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_91net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_109net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_55net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_73net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_19net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_37net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_118net (fanout=1) 3.877 CACHE_UNIT/dc/M_VCC/I_118_n_1Tilo 0.468 CACHE_UNIT/dc/M_VCC/VC_Hit1net (fanout=20) 2.357 CACHE_UNIT/dc/VC_Data_Sel[1]Tilo 0.468 CACHE_UNIT/dc/M_VCC/VC_Hitnet (fanout=26) 5.002 CACHE_UNIT.VC_HitTilo 0.468 CACHE_UNIT/dcc/request_0_i_0_onet (fanout=5) 1.153 CACHE_UNIT/dcc/N_428Tilo 0.468 CACHE_UNIT/dcc/G_286net (fanout=11) 4.903 CACHE_UNIT/N_497Tilo 0.468 CACHE_UNIT/dc/un1_reg_ennet (fanout=2) 8.948 CACHE_UNIT/dc/un1_reg_en_nTbeck 2.418 CACHE_UNIT/dc/dtf/B5.A---------------------------- ---------------------------Total 36.762ns (7.644ns logic, 29.118ns route(20.8% logic, 79.2% route)------------------------------------------------------------Delay: 36.786ns (data path - clock path skeSource: DP/S1_dff/Q[7] (FF)Destination: CACHE_UNIT/dc/dtf/B9.A (RAM)Data Path Delay: 36.745ns (Levels of Logic = 12)Clock Path Skew: -0.041nsSource Clock: processor_clock risingDestination Clock: processor_clock risingClock Uncertainty: 0.000nsData Path: DP/S1_dff/Q[7] to CACHE_UNIT/dc/dtf/B9.ADelay type Delay(ns) Logical Resource(s)---------------------------- -------------------Tcko 0.992 DP/S1_dff/Q[7]net (fanout=50) 2.878 S1[7]Topcyg 1.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_91net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_109net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_55net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_73net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_19net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_37net (fanout=1) 0.000 CACHE_UNIT/dc/M_VCC/un2_VC_HitTbyp 0.149 CACHE_UNIT/dc/M_VCC/un2_VC_HitCACHE_UNIT/dc/M_VCC/un2_VC_Hit1_0.I_118net (fanout=1) 3.877 CACHE_UNIT/dc/M_VCC/I_118_n_1Tilo 0.468 CACHE_UNIT/dc/M_VCC/VC_Hit1net (fanout=20) 2.357 CACHE_UNIT/dc/VC_Data_Sel[1]Tilo 0.468 CACHE_UNIT/dc/M_VCC/VC_Hitnet (fanout=26) 5.002 CACHE_UNIT.VC_HitTilo 0.468 CACHE_UNIT/dcc/request_0_i_0_onet (fanout=5) 1.153 CACHE_UNIT/dcc/N_428Tilo 0.468 CACHE_UNIT/dcc/G_286net (fanout=11) 4.903 CACHE_UNIT/N_497Tilo 0.468 CACHE_UNIT/dc/un1_reg_ennet (fanout=2) 8.931 CACHE_UNIT/dc/un1_reg_en_nTbeck 2.418 CACHE_UNIT/dc/dtf/B9.A---------------------------- ---------------------------Total 36.745ns (7.644ns logic, 29.101ns route(20.8% logic, 79.2% route)------------------------------------------------------------Delay: 36.707ns (data path - clock path skeSource: CACHE_UNIT/dc/dtf/B5.B (RAM)Destination: CACHE_UNIT/dc/dtf/B9.A (RAM)Data Path Delay: 36.694ns (Levels of Logic = 8)Clock Path Skew: -0.013nsSource Clock: processor_clock risingDestination Clock: processor_clock risingClock Uncertainty: 0.000nsData Path: CACHE_UNIT/dc/dtf/B5.B to CACHE_UNIT/dc/dtf/B9.ADelay type Delay(ns) Logical Resource(s)---------------------------- -------------------Tbcko 3.414 CACHE_UNIT/dc/dtf/B5.Bnet (fanout=2) 4.973 CACHE_UNIT/dc/tf_dout1[2]Topcyg 1.000 CACHE_UNIT/dc/un3_DT1Hit_0.I_9CACHE_UNIT/dc/un3_DT1Hit_0.I_82net (fanout=1) 0.000 CACHE_UNIT/dc/un3_DT1Hit_0.I_8Tbyp 0.149


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Berkeley COMPSCI 152 - CS 152 Final Project

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