CS152 Computer Architecture and Engineering Lecture 12 Exceptions (continued) Introduction to PipeliningRecap: MicroprogrammingSlide 3Recap: Multicycle datapath (book)Recap: Start with List of control signalsRecap: Group together related signalsRecap: Group into Fields, Order and Assign NamesRecap: Quick check: what do these fieldnames mean?Recap: Finite State Machine (FSM) SpecRecap: Microprogram it yourself!Recap: Specific Sequencer from last lectureExceptionsTwo Types of Exceptions: Interrupts and TrapsPrecise ExceptionsBig Picture: user / system modesAdministriviaAddressing the Exception HandlerSaving StateAdditions to MIPS ISA to support Exceptions?Details of Status registerDetails of Cause registerPart of the handler in trap_handler.sExample: How Control Handles Traps in our FSDHow add traps and interrupts to state diagram?But: What has to change in our -sequencer?Example: Can easily use with for non-ideal memoryQuestion #1: Why do microcoding?Recall: Performance EvaluationQuestion #2: Can we get CPI < 4.1?The Big Picture: Where are We Now?Pipelining is Natural!Sequential LaundryPipelined Laundry: Start work ASAPPipelining LessonsThe Five Stages of LoadNote: These 5 stages were there all along!PipeliningBasic IdeaGraphically Representing PipelinesConventional Pipelined Execution RepresentationSingle Cycle, Multiple Cycle, vs. PipelineWhy Pipeline?Why Pipeline? Because we can!Can pipelining get us into trouble?Single Memory is a Structural HazardStructural Hazards limit performanceControl Hazard Solution #1: StallControl Hazard Solution #2: PredictControl Hazard Solution #3: Delayed BranchData Hazard on r1Data Hazard on r1:Data Hazard Solution:Forwarding (or Bypassing): What about Loads?Forwarding (or Bypassing): What about LoadsDesigning a Pipelined ProcessorControl and Datapath: Split state diag into 5 piecesSummary: ExceptionsSummary: PipeliningSummary: Where this class is going3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.1CS152Computer Architecture and EngineeringLecture 12Exceptions (continued)Introduction to PipeliningMarch 10, 2003John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.2Recap: Microprogramming°Microprogramming is a fundamental concept•implement an instruction set by building a very simple processor and interpreting the instructions•essential for very complex instructions and when few register transfers are possible•overkill when ISA matches datapath 1-1sequencercontroldatapath controlmicro-PC-sequencer:fetch,dispatch,sequentialmicroinstruction ()DispatchROMOpcode-Code ROMDecodeDecodeTo DataPathDecoders implement our -code language:For instance:rt-ALUrd-ALUmem-ALU3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.3Recap: Microprogramming°Microprogramming is a convenient method for implementing structured control state diagrams:•Random logic replaced by microPC sequencer and ROM•Each line of ROM called a instruction: contains sequencer control + values for control points•limited state transitions: branch to zero, next sequential,branch to instruction address from displatch ROM°Design of a Microprogramming language1.Start with list of control signals2.Group signals together that make sense (vs. random): called “fields”3.Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)4.To minimize the width, encode operations that will never be used at the same time5.Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.4Recap: Multicycle datapath (book)IdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCond PCSrc32IorDMem Data RegALU OutBAMemRd3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.5Recap: Start with List of control signalsSignal name Effect when deasserted Effect when assertedALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRead None Memory at address is read, MDR <= Mem[addr]MemWrite None Memory at address is written IorD Memory address = PC Memory address = SIRWrite None IR <= MemoryPCWrite None PC <= PCSourcePCWriteCond None IF ALUzero then PC <= PCSourcePCSource PCSource = ALU PCSource = ALUoutExtOp Zero Extended Sign Extended Single Bit ControlSignal name Value Effect ALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code11 ALU does logical OR ALUSelB 00 2nd ALU input = 4 01 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extendedMultiple Bit Control3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.6Recap: Group together related signalsIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCond PCSrc32IorDMem Data RegALU OutBAMemRdALUSRC1SRC2DestinationMemoryPCWrite3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.7Recap: Group into Fields, Order and Assign NamesField Name Values for Field Function of Field with Specific ValueALU Add ALU addsSubt. ALU subtractsFunc ALU does function codeOr ALU does logical ORSRC1 PC 1st ALU input <= PCrs 1st ALU input <= Reg[rs]SRC2 4 2nd ALU input <= 4Extend 2nd ALU input <= sign ext. IR[15-0]Extend0 2nd ALU input <= zero ext. IR[15-0] Extshft 2nd ALU input <= sign ex., sl IR[15-0]rt 2nd ALU input <= Reg[rt]dest(ination) rd ALU Reg[rd] <= ALUout rt ALU Reg[rt] <= ALUout rt Mem Reg[rt] <= Mem Mem(ory) Read PC Read memory using PCRead ALU Read memory using ALUout for addrWrite ALU Write memory using ALUout for addrMemreg IR IR <= MemPCwrite PCwr PC <= PCSourcePCSrc IF Zero then PCSource <= ALUout else ALUPCWrCond IF Zero then PC <= PCSource Seq(uencing) Seq Go to next sequential µinstructionFetch Go to the first microinstructionDispatch Dispatch using ROM.ALU SRC1SRC2Dest Mem Memreg PCwrite Seq3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.8Recap: Quick check: what do these fieldnames mean?Code
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