CS152 Computer Architecture and Engineering Lecture 12 Exceptions continued Introduction to Pipelining March 10 2003 John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 3 10 03 UCB Spring 2003 CS152 Kubiatowicz Recap Microprogramming sequencer datapath control control Code ROM microinstruction micro PC Opcode sequencer fetch dispatch sequential Dispatch ROM Decode Decode Decoders implement our code language For instance rt ALU rd ALU mem ALU To DataPath Microprogramming is a fundamental concept implement an instruction set by building a very simple processor and interpreting the instructions essential for very complex instructions and when few register transfers are possible overkill when ISA matches datapath 1 1 3 10 03 UCB Spring 2003 CS152 Kubiatowicz Recap Microprogramming Microprogramming is a convenient method for implementing structured control state diagrams Random logic replaced by microPC sequencer and ROM Each line of ROM called a instruction contains sequencer control values for control points limited state transitions branch to zero next sequential branch to instruction address from displatch ROM Design of a Microprogramming language 1 Start with list of control signals 2 Group signals together that make sense vs random called fields 3 Place fields in some logical order e g ALU operation ALU operands first and microinstruction sequencing last 4 To minimize the width encode operations that will never be used at the same time 5 Create a symbolic legend for the microinstruction format showing name of field values and how they set the control signals 3 10 03 UCB Spring 2003 CS152 Kubiatowicz Recap Multicycle datapath book PCWr PCSrc RegDst ALUSelA RegWr 32 PC 32 32 5 Rt 0 Rd Rb busA A Reg File Rw busW busB 1 1 Mux 0 Imm 16 1 4 B 2 Extend ExtOp 3 10 03 Ra 32 32 0 32 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2003 Zero ALU Out WrAdr 32 Din Dout 32 Rt Mux Ideal Memory 1 5 32 ALU 32 Rs Mem Data Reg Mux RAdr 0 Mux 0 32 Instruction Reg 32 1 Mux PCWrCond Zero IorD MemWr IRWr MemRd ALUOp ALUSelB CS152 Kubiatowicz Multiple Bit Control Single Bit Control Recap Start with List of control signals Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand PC 1st ALU operand Reg rs RegWrite None Reg is written MemtoReg Reg write data input ALU Reg write data input memory RegDst Reg dest no rt Reg dest no rd MemRead None Memory at address is read MDR Mem addr MemWrite None Memory at address is written IorD Memory address PC Memory address S IRWrite None IR Memory PCWrite None PC PCSource PCWriteCond None IF ALUzero then PC PCSource PCSource PCSource ALU PCSource ALUout ExtOp Zero Extended Sign Extended Signal name Value ALUOp 00 01 10 11 ALUSelB 00 01 10 11 3 10 03 Effect ALU adds ALU subtracts ALU does function code ALU does logical OR 2nd ALU input 4 2nd ALU input Reg rt 2nd ALU input extended shift left 2 2nd ALU input extended UCB Spring 2003 CS152 Kubiatowicz Recap Group together related signals PCWr PCWrite PCWrCond Destination Memory Zero IorD MemWr IRWr RegDst RegWr MemRd PCSrc SRC1 32 PC 32 32 5 Rt 0 Rd busA A Reg File Rw busW busB 1 1 4 B 2 Extend ExtOp SRC2 Rb 1 Mux 0 Imm 16 3 10 03 Ra 32 32 0 32 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2003 Zero ALU Out WrAdr 32 Din Dout 32 Rt Mux Ideal Memory 1 5 32 ALU 32 Rs Mem Data Reg Mux RAdr 0 Mux 0 32 Instruction Reg 32 1 Mux ALUSelA ALUOp ALU ALUSelB CS152 Kubiatowicz Recap Group into Fields Order and Assign Names ALU SRC 1 Field Name ALU SRC1 SRC2 dest ination Mem ory Memreg PCwrite Seq uencing 3 10 03 SRC Dest Mem Memreg 2 PCwrite Seq Values for Field Function of Field with Specific Value Add ALU adds Subt ALU subtracts Func ALU does function code Or ALU does logical OR PC 1st ALU input PC rs 1st ALU input Reg rs 4 2nd ALU input 4 Extend 2nd ALU input sign ext IR 15 0 Extend0 2nd ALU input zero ext IR 15 0 Extshft 2nd ALU input sign ex sl IR 15 0 rt 2nd ALU input Reg rt rd ALU Reg rd ALUout rt ALU Reg rt ALUout rt Mem Reg rt Mem Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addr IR IR Mem PCwr PC PCSource PCSrc IF Zero then PCSource ALUout else ALU PCWrCond IF Zero then PC PCSource Seq Go to next sequential instruction CS152 Kubiatowicz UCB Spring Fetch Go to 2003 the first microinstruction Dispatch Dispatch using ROM Recap Quick check what do these fieldnames mean Destination Code Name 00 0 01rd ALU 1 10rt ALU 1 11rt MEM 1 RegWrite X 0 0 1 MemToReg X 1 0 0 ALUSelB X 00 01 10 11 11 ExtOp X X X 1 1 0 RegDest SRC2 Code 000 001 010 011 100 111 3 10 03 Name 4 rt ExtShft Extend Extend0 UCB Spring 2003 CS152 Kubiatowicz Recap Finite State Machine FSM Spec IR MEM PC PC PC 4 0000 ALUout PC SX instruction fetch decode 0001 ALUout A fun B 0100 ORi ALUout A or ZX 0110 LW ALUout A SX 1000 M MEM ALUout 1001 R rd ALUout 0101 3 10 03 R rt ALUout 0111 BEQ SW ALUout A SX 1011 MEM ALUout B 1100 R rt M 1010 UCB Spring 2003 If A B then PC ALUout 0010 Memory Write back Execute R type CS152 Kubiatowicz Recap Microprogram it yourself AddrALU SRC1 SRC2 Dest Memory Fetch 0000 AddPC 4 0001 AddPC Extshft Read PC Dispatch BEQ 0010 Subt rs Rtype 0100 Func 0101 rd ALU rs rt Fetch rt Mem Reg PC Write Sequencing IR ALUoutCond ALU Seq Fetch Seq ORI 0110 Or rs Extend0 Seq 0111 rt ALU Fetch LW 1000 Addrs Extend Seq 1001 Read ALU Seq 1010 rt MEM Fetch SW 1011 Addrs Extend Seq 1100 Write ALU Fetch 3 10 03 UCB Spring 2003 CS152 Kubiatowicz Recap Specific Sequencer from last lecture Sequencer based control unit from last lecture Called microPC or PC vs state register Code Name Effect 00 fetch Next address 0 01 dispatch Next address dispatch ROM 10 seq Next address address 1 ROM 3 10 03 Opcode Dispatch state 000000 Rtype 0100 000100 BEQ 0010 001101 ORI 0110 100011 LW 1000 101011 SW 1011 1 Adder Address Select Logic UCB Spring 2003 microPC Mux 2 1 0 0 ROM Opcode CS152 Kubiatowicz Exceptions user program Exception System Exception Handler return from exception normal control flow sequential jumps branches calls returns Exception unprogrammed control transfer system takes action to handle the exception must record the address of the offending instruction record any other information necessary to return afterwards returns control to user must save restore user state Allows constuction of a user virtual machine CS152 Kubiatowicz 3 10 03 UCB Spring 2003 Two Types of Exceptions Interrupts and Traps …
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