CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design March 5 2003 John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Review High Level Design Design Process Design Entry Schematics HDL Compilers High Level Analysis Simulation Testing Assertions Technology Mapping Turn design into physical implementation Low Level Analysis Check out Timing Setup Hold etc Verilog Three programming styles Structural Like a Netlist Instantiation of modules wires between them Dataflow Higher Level Expressions instead of gates Behavioral Hardware programming Full flow control mechanisms 3 05 03 Registers variables File I O consol display etc UCB Spring 2003 CS152 Kubiatowicz Review Testing Make sure that things work Testing methodologies Alewife Numbers Understand what correct behavior is when you design things Collect vectors for later use Build monitor modules to check assertions of correct values Produce a regression test Set of tests to run each time something changes Types of test Doug Clark Directed Vectors test explicit behavior Random Vectors apply random values or orderings to device Daemons continuous error insertion Monitor modules Check to see if invariants are maintained during long running simulations 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Review Monitor Modules Passthrough testing module monitorsum32 carry sum A B input 31 0 A B output 31 0 sum output carry reg 31 0 predsum reg precarry The real adder sum32 mysum carry sum A B ifndef synthesis This checker code only for simulation always A or B begin 100 wait for output to settle don t make too long predcarry predsum A B if carry predcarry sum predsum display Mismatch 0x x 0x x 0x x carry x A B sum carry end endif endmodule 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Lab4 version monitors and benches Idea wrap testing infrastructure around devices under test DUT Include test vectors that are supposed to detect errors in implementation Even strange ones Can and probably should in later labs include assert statements to check for things that should never happen Complete Top Level Design Test Bench Device Under Test Inline Monitor Output in readable format disassembly Assert Statements Inline vectors Assert Statements File IO either for patterns or output diagnostics 3 05 03 UCB Spring 2003 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topics Microprogramed control Administrivia Courses Microprogram it yourself Exceptions Intro to Pipelining if time permits 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Alternative multicycle datapath book Miminizes Hardware 1 memory 1 adder PCWr PCSrc RegDst ALUSelA RegWr 32 PC 32 32 5 Rt 0 Rd Rb busA A Reg File Rw busW busB 1 1 Mux 0 Imm 16 1 4 B 2 Extend ExtOp 3 05 03 Ra 32 32 0 32 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2003 Zero ALU Out WrAdr 32 Din Dout 32 Rt Mux Ideal Memory 1 5 32 ALU 32 Rs Mem Data Reg Mux RAdr 0 Mux 0 32 Instruction Reg 32 1 Mux PCWrCond Zero IorD MemWr IRWr ALUOp ALUSelB CS152 Kubiatowicz New Finite State Machine FSM Spec PC PC 4 0000 instruction fetch decode Q How improve to do something in state 0001 0001 R type ALUout A fun B 0100 ORi ALUout A or ZX 0110 LW ALUout A SX 1000 M MEM ALUout 1001 R rd ALUout 0101 3 05 03 R rt ALUout 0111 BEQ SW ALUout A SX 1011 MEM ALUout B 1100 R rt M 1010 UCB Spring 2003 ALUout PC SX 0010 If A B then PC ALUout 0011 Memory Write back Execute IR MEM PC CS152 Kubiatowicz Finite State Machine FSM Spec IR MEM PC PC PC 4 0000 ALUout PC SX instruction fetch decode 0001 ALUout A fun B 0100 ORi ALUout A or ZX 0110 LW ALUout A SX 1000 M MEM ALUout 1001 R rd ALUout 0101 3 05 03 R rt ALUout 0111 BEQ SW ALUout A SX 1011 MEM ALUout B 1100 R rt M 1010 UCB Spring 2003 If A B then PC ALUout 0010 Memory Write back Execute R type CS152 Kubiatowicz Recap Microprogramming sequencer datapath control control Inputs Code ROM microinstruction micro PC Opcode sequencer fetch dispatch sequential Dispatch ROM Decode Decode To DataPath Microprogramming is a fundamental concept implement an instruction set by building a very simple processor and interpreting the instructions essential for very complex instructions and when few register transfers are possible overkill when ISA matches datapath 1 1 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Recap Microprogramming Microprogramming is a convenient method for implementing structured control state diagrams Random logic replaced by microPC sequencer and ROM Each line of ROM called a instruction contains sequencer control values for control points limited state transitions branch to zero next sequential branch to instruction address from displatch ROM Horizontal Code one control bit in Instruction for every control line in datapath Vertical Code groups of control lines coded together in Instruction e g possible ALU dest Control design reduces to Microprogramming Part of the design process is to develop a language that describes control and is easy for humans to understand 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Recap Macroinstruction Interpretation Main Memory ADD SUB AND DATA execution unit CPU User program plus Data this can change one of these is mapped into one of these AND microsequence control memory e g Fetch Calc Operand Addr Fetch Operand s Calculate Save Answer s 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Designing a Microinstruction Set 1 Start with list of control signals 2 Group signals together that make sense vs random called fields 3 Place fields in some logical order e g ALU operation ALU operands first and microinstruction sequencing last 4 To minimize the width encode operations that will never be used at the same time 5 Create a symbolic legend for the microinstruction format showing name of field values and how they set the control signals Use computers to design computers 3 05 03 UCB Spring 2003 CS152 Kubiatowicz Again Alternative multicycle datapath book Miminizes Hardware 1 memory 1 adder PCWr PCSrc RegDst ALUSelA RegWr 32 PC 32 32 5 Rt 0 Rd Rb busA A Reg File Rw busW busB 1 1 Mux 0 Imm 16 1 4 B 2 Extend ExtOp 3 05 03 Ra 32 32 0 32 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2003 Zero ALU Out WrAdr 32 Din Dout 32 Rt Mux Ideal Memory 1 5 32 ALU 32 Rs Mem Data Reg Mux RAdr 0 Mux 0 32 Instruction Reg 32 1 Mux PCWrCond Zero IorD MemWr IRWr ALUOp ALUSelB CS152 Kubiatowicz Multiple Bit
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