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Berkeley COMPSCI 152 - Lecture 4 - Pipelining

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January 31, 2011 CS152, Spring 2011 CS 152 Computer Architecture and Engineering Lecture 4 - Pipelining Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!http://inst.eecs.berkeley.edu/~cs152!January 31, 2011 CS152, Spring 2011 2 Last time in Lecture 3 • Microcoding became less attractive as gap between RAM and ROM speeds reduced • Complex instruction sets difficult to pipeline, so difficult to increase performance as gate count grew • Iron Law explains architecture design space – Trade instructions/program, cycles/instruction, and time/cycle • Load-Store RISC ISAs designed for efficient pipelined implementations – Very similar to vertical microcode – Inspired by earlier Cray machines (more on these later)January 31, 2011 CS152, Spring 2011 3 An Ideal Pipeline • All objects go through the same stages • No sharing of resources between any two stages • Propagation delay through all pipeline stages is equal • The scheduling of an object entering the pipeline is not affected by the objects in other stages stage 1 stage 2 stage 3 stage 4 These conditions generally hold for industrial assembly lines, but instructions depend on each other!January 31, 2011 CS152, Spring 2011 4 Pipelined MIPS To pipeline MIPS: • First build MIPS without pipelining with CPI=1 • Next, add pipeline registers to reduce cycle time while maintaining CPI=1January 31, 2011 CS152, Spring 2011 5 Lecture 3: Unpipelined Datapath for MIPS 0x4 RegWrite Add Add clk WBSrc MemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSel OpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU ALU Control 31 PCSrc br rind jabs pc+4January 31, 2011 CS152, Spring 2011 6 Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc ALU ALUi ALUiu LW SW BEQZz=0 BEQZz=1 J JAL JR JALR Lecture 3: Hardwired Control Table BSrc = Reg / Imm WBSrc = ALU / Mem / PC RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs * * * no yes rind PC R31 rind * * * no no * * jabs * * * no yes PC R31 jabs * * * no no * * pc+4 sExt16 * 0? no no * * br sExt16 * 0? no no * * pc+4 sExt16 Imm + yes no * * pc+4 Imm Op no yes ALU rt pc+4 * Reg Func no yes ALU rd sExt16 Imm Op pc+4 no yes ALU rt pc+4 sExt16 Imm + no yes Mem rt uExt16January 31, 2011 CS152, Spring 2011 7 Pipelined Datapath Clock period can be reduced by dividing the execution of an instruction into multiple cycles tC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably) However, CPI will increase unless instructions are pipelined write -back phase fetch phase execute phase decode & Reg-fetch phase memory phase addr wdata rdata Data Memory we ALU Imm Ext 0x4 Add addr rdata Inst. Memory rd1 GPRs rs1 rs2 ws wd rd2 we IR PCJanuary 31, 2011 CS152, Spring 2011 8 “Iron Law” of Processor Performance Time = Instructions Cycles Time Program Program * Instruction * Cycle – Instructions per program depends on source code, compiler technology, and ISA – Cycles per instructions (CPI) depends upon the ISA and the microarchitecture – Time per cycle depends upon the microarchitecture and the base technology Microarchitecture CPI cycle time Microcoded >1 short Single-cycle unpipelined 1 long Pipelined 1 short Lecture 2 Lecture 3 Lecture 4January 31, 2011 CS152, Spring 2011 CPI Examples 9 Time Inst 3 7 cycles Inst 1 Inst 2 5 cycles 10 cycles Microcoded machine 3 instructions, 22 cycles, CPI=7.33 Unpipelined machine 3 instructions, 3 cycles, CPI=1 Inst 1 Inst 2 Inst 3 Pipelined machine 3 instructions, 3 cycles, CPI=1 Inst 1 Inst 2 Inst 3January 31, 2011 CS152, Spring 2011 10 Technology Assumptions Thus, the following timing assumption is reasonable • A small amount of very fast memory (caches) backed up by a large, slower memory • Fast ALU (at least for integers) • Multiported Register files (slower!) tIM ≈ tRF ≈ tALU ≈ tDM ≈ tRW A 5-stage pipeline will be the focus of our detailed design - some commercial designs have over 30 pipeline stages to do an integer add!January 31, 2011 CS152, Spring 2011 11 5-Stage Pipelined Execution time t0 t1 t2 t3 t4 t5 t6 t7 . . . . instruction1 IF1 ID1 EX1 MA1 WB1 instruction2 IF2 ID2 EX2 MA2 WB2 instruction3 IF3 ID3 EX3 MA3 WB3 instruction4 IF4 ID4 EX4 MA4 WB4 instruction5 IF5 ID5 EX5 MA5 WB5 Write -Back (WB) I-Fetch (IF) Execute (EX) Decode, Reg. Fetch (ID) Memory (MA) addr wdata rdata Data Memory we ALU Imm Ext 0x4 Add addr rdata Inst. Memory rd1 GPRs rs1 rs2 ws wd rd2 we IR PCJanuary 31, 2011 CS152, Spring 2011 12 5-Stage Pipelined Execution Resource Usage Diagram time t0 t1 t2 t3 t4 t5 t6 t7 . . . . IF I1 I2 I3 I4 I5 ID I1 I2 I3 I4 I5 EX I1 I2 I3 I4 I5 MA I1 I2 I3 I4 I5 WB I1 I2 I3 I4 I5 Resources Write -Back (WB) I-Fetch (IF) Execute (EX) Decode, Reg. Fetch (ID) Memory (MA) addr wdata rdata Data Memory we ALU Imm Ext 0x4 Add addr rdata Inst. Memory rd1 GPRs rs1 rs2 ws wd rd2 we IR PCJanuary 31, 2011 CS152, Spring 2011 13 Pipelined Execution: ALU Instructions IR IR IR 31 PC A B Y R MD1 MD2 addr inst Inst Memory 0x4 Add IR Imm Ext ALU rd1 GPRs rs1 rs2 ws wd rd2 we wdata addr wdata rdata Data Memory we Not quite correct! We need an Instruction Reg (IR) for each stageJanuary 31, 2011 CS152, Spring 2011 14 Pipelined MIPS Datapath without jumps IR IR IR 31 PC A B Y R MD1 MD2 addr inst Inst Memory 0x4 Add IR Imm Ext ALU rd1 GPRs rs1 rs2 ws wd rd2 we Data Memory wdata addr wdata rdata we OpSel ExtSel BSrc WBSrc MemWrite RegDst RegWrite F D E M W Control Points Need to Be ConnectedJanuary 31, 2011 CS152, Spring 2011 15 Instructions interact with each other in pipeline • An instruction in the pipeline may need a resource being used by another instruction in the pipeline  structural hazard • An instruction may depend on something produced by an earlier instruction – Dependence may be for a data value  data hazard – Dependence may be for the next instruction’s address  control hazard (branches, exceptions)January 31, 2011 CS152, Spring 2011 Resolving Structural Hazards • Structural hazards occurs when two instruction need same hardware resource at same time – Can resolve in hardware by stalling newer instruction till


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