CS152 Computer Architecture and Engineering Lecture 10 High-Level Design/ Microcode programmingRecap: What’s wrong with our CPI=1 processor?Recap: Partitioning the CPI=1 DatapathRecap: Example Multicycle DatapathRecap: FSM specificationRecap: Micro-controller DesignRecap: Specific Sequencer from last lectureRecap: Microprogram Control SpecificationRepresentation LanguagesSimulation Before ConstructionLevels of DescriptionNetlistDesign FlowSlide 14Slide 15Slide 16Slide 17Design EntryHigh Level Design Languages (HDLs)AdministrationVerilog HistoryBasic Example: 2-to1 mux in Structural Form2-1 Mux in Dataflow Form2-to-1 mux Behavioral descriptionCombining modules: Hierarchy & Bit VectorsBehavioral 4-to1 muxBehavioral with Bit VectorsDelay SpecificationsSequential LogicTesting: Make sure that things workMonitor Modules: Passthrough testingTestbench: Applying Directed VectorsTestbench: Randomized Vector TestingMore Verilog HelpThe Big Picture: Where are We Now?Microprogramming (Maurice Wilkes)Instruction Set Architecture (subset of Computer Arch.)“Macroinstruction” InterpretationVariations on MicroprogrammingExtreme HorizontalMore Vertical FormatHybrid ControlVax MicroinstructionsHorizontal vs. Vertical MicroprogrammingHow Effectively are we utilizing our hardware?“Princeton” OrganizationAlternative datapath (book)Summary ISummary II3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.1CS152Computer Architecture and Engineering Lecture 10 High-Level Design/Microcode programmingMarch 3, 2002John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.2Recap: What’s wrong with our CPI=1 processor?°Long Cycle Time°All instructions take as much time as the slowest°Real memory is not as nice as our idealized memory•cannot always get the job done in one (short) cyclePC Inst MemorymuxALU Data MemmuxPC Reg FileInst MemorymuxALUmuxPC Inst MemorymuxALU Data MemPC Inst Memory cmpmuxReg FileReg FileReg FileArithmetic & LogicalLoadStoreBranchCritical Pathsetupsetup3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.3Recap: Partitioning the CPI=1 Datapath°Add registers between smallest steps°Place enables on all registersPCNext PCOperandFetchExecReg. FileMemAccessDataMemInstructionFetchResult StoreALUctrRegDstALUSrcExtOpMemWrnPC_selRegWrMemWrMemRdEqual3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.4Recap: Example Multicycle Datapath°Critical Path ?PCNext PCOperandFetchInstructionFetchnPC_selIRRegFileExtALUReg. FileMemAccessDataMemResult StoreRegDstRegWrMemWrMemRdSMMemToRegEqualALUctrALUSrcExtOpABE3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.5Recap: FSM specificationIR <= MEM[PC]R-typeA <= R[rs]B <= R[rt]S <= A fun BR[rd] <= SPC <= PC + 4S <= A or ZXR[rt] <= SPC <= PC + 4ORiS <= A + SXR[rt] <= MPC <= PC + 4M <= MEM[S]LWS <= A + SXMEM[S] <= BPC <= PC + 4BEQPC <= Next(PC)SW“instruction fetch”“decode”000000010100010101100111100010011010001110111100ExecuteMemoryWrite-back3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.6Recap: Micro-controller Design°The state digrams that arise define the controller for an instruction set processor are highly structured°Use this structure to construct a simple “microsequencer” •Each state in previous diagram becomes a “microinstruction”•Microinstructions often taken sequentially°Control reduces to programming this devicesequencercontroldatapath controlmicro-PCsequencermicroinstruction ()3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.7Recap: Specific Sequencer from last lecture°Sequencer-based control unit from last lecture•Called “microPC” or “µPC” vs. state registerControl Value Effect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1ROM: OpcodemicroPC1µAddressSelectLogicAdderROMMux0012R-type 000000 0100BEQ 000100 0011ori 001101 0110LW 100011 1000SW 101011 10113/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.8Recap: Microprogram Control Specification0000 ? inc 10001 x load 1 10011 0 zero 1 00011 1 zero 1 10100 x inc 0 1 fun 10101 x zero 1 0 0 1 10110 x inc 0 0 or 10111 x zero 1 0 0 1 01000 x inc 1 0 add 11001 x inc 1 0 11010 x zero 1 0 1 1 01011 x inc 1 0 add 11100 x zero 1 0 0 1 0µPC Taken Next IR PC Ops Exec Mem Write-Backen sel A B Ex Sr ALU S R W M M-R Wr DstR:ORi:LW:SW:BEQ3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.9Hardware Representation Languages: Block Diagrams: FUs, Registers, & Dataflows Register Transfer Diagrams: Choice of busses to connect FUs, Regs Flowcharts State DiagramsFifth Representation "Language": Hardware Description Languages E.G., ISP' VHDL VerilogDescriptions in these languages can be used as input to simulation systems synthesis systemsRepresentation LanguagesTwo different ways to describe sequencing & microoperationshw modules described like programswith i/o ports, internal state, & parallelexecution of assignment statements"software breadboard"generate hw from high level description"To Design is to Represent"3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.10Simulation Before Construction"Physical Breadboarding" discrete components/lower scale integration preceeds actual construction of prototype verify initial design conceptNo longer possible as designs reach higher levels of integration!Simulation Before Construction high level constructs implies faster to construct play "what if" more easily limited performance accuracy, however3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.11Levels of DescriptionArchitectural SimulationFunctional/Behavioral/DataflowRegister TransferLogicCircuitmodels programmer's view at ahigh level; written in your favoriteprogramming languagemore detailed model, like theblock diagram viewcommitment to datapath FUs,registers, busses; register xferoperations are clock phase accuratemodel is in terms of logic gates;higher level MSI functionsdescribed in terms of theseelectrical behavior; accuratewaveformsSchematic capture + logic simulation package like Xilinx ISESpecial languages + simulation systems for describing the inherent parallel activity in hardwareLess AbstractMore AccurateSlower Simulation3/3/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec10.12Netlist°A key data structure (or representation) in the design process is the “netlist”:•Network List°A netlist
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