CS152 Computer Architecture and Engineering Lecture 10 High Level Design Microcode programming March 3 2002 John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 3 3 03 UCB Spring 2003 CS152 Kubiatowicz Recap What s wrong with our CPI 1 processor Arithmetic Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory ALU Data Mem Store PC mux Reg File Critical Path Inst Memory Reg File ALU Data Mem Branch PC Inst Memory Reg File mux cmp mux setup mux Long Cycle Time All instructions take as much time as the slowest Real memory is not as nice as our idealized memory cannot always get the job done in one short cycle 3 3 03 UCB Spring 2003 CS152 Kubiatowicz 3 3 03 Operand Fetch Instruction Fetch PC Next PC Exec UCB Spring 2003 Reg File Result Store Data Mem Mem Access MemWr RegDst RegWr MemRd MemWr ALUctr ALUSrc ExtOp Equal nPC sel Add registers between smallest steps Recap Partitioning the CPI 1 Datapath CS152 Kubiatowicz 3 3 03 ExtOp Equal B UCB Spring 2003 S Reg File RegDst RegWr MemToReg MemRd MemWr ALUctr Ext ALUSrc ALU A Result Store Reg File Mem Access IR nPC sel E Data Mem Operand Fetch Instruction Fetch PC Next PC Recap Example Multicycle Datapath M Critical Path CS152 Kubiatowicz Recap FSM specification instruction fetch IR MEM PC 0000 decode A R rs B R rt S A fun B 0100 ORi S A or ZX 0110 LW S A SX 1000 M MEM S 1001 SW BEQ S A SX 1011 MEM S B PC PC 4 1100 R rd S R rt S R rt M PC PC 4 PC PC 4 PC PC 4 0101 3 3 03 0111 1010 UCB Spring 2003 PC Next PC 0011 Write back Memory R type Execute 0001 CS152 Kubiatowicz Recap Micro controller Design The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer Each state in previous diagram becomes a microinstruction Microinstructions often taken sequentially Control reduces to programming this device sequencer control datapath control microinstruction micro PC 3 3 03 sequencer UCB Spring 2003 CS152 Kubiatowicz Recap Specific Sequencer from last lecture Sequencer based control unit from last lecture Called microPC or PC vs state register Control Value Effect 00 Next address 0 01 Next address dispatch ROM 10 Next address address 1 1 Adder ROM 3 3 03 R type BEQ ori LW SW 000000 000100 001101 100011 101011 0100 0011 0110 1000 1011 UCB Spring 2003 Address Select Logic microPC Mux 2 1 0 0 ROM Opcode CS152 Kubiatowicz Recap Microprogram Control Specification PC Taken 0000 0001 x 0011 0011 R 0100 0101 ORi 0110 0111 1000 LW 1001 1010 SW 1011 1100 BEQ 3 3 03 0 1 x x x x x x x x x Next IR PC Ops Exec Mem Write Back en sel A B Ex Sr ALU S R W M M R Wr Dst inc load 1 11 zero zero inc zero inc zero inc inc zero inc zero 1 1 0 1 0 1 1 1 1 1 0 1 1 fun 1 0 0 1 1 0 or 1 0 0 1 0 0 add 1 0 1 0 1 1 0 0 add 1 1 0 0 1 0 UCB Spring 2003 CS152 Kubiatowicz Representation Languages Hardware Representation Languages Block Diagrams FUs Registers Dataflows Register Transfer Diagrams Choice of busses to connect FUs Regs Flowcharts Two different ways to describe sequencing microoperations State Diagrams Fifth Representation Language Hardware Description Languages hw modules described like programs with i o ports internal state parallel execution of assignment statements E G ISP VHDL Verilog Descriptions in these languages can be used as input to simulation systems software breadboard synthesis systems generate hw from high level description To Design is to Represent 3 3 03 UCB Spring 2003 CS152 Kubiatowicz Simulation Before Construction Physical Breadboarding discrete components lower scale integration preceeds actual construction of prototype verify initial design concept No longer possible as designs reach higher levels of integration Simulation Before Construction high level constructs implies faster to construct play what if more easily limited performance accuracy however 3 3 03 UCB Spring 2003 CS152 Kubiatowicz Levels of Description Architectural Simulation models programmer s view at a high level written in your favorite programming language Functional Behavioral Dataflow more detailed model like the block diagram view Register Transfer commitment to datapath FUs registers busses register xfer operations are clock phase accurate Logic model is in terms of logic gates higher level MSI functions described in terms of these Circuit Less Abstract More Accurate Slower Simulation electrical behavior accurate waveforms Schematic capture logic simulation package like Xilinx ISE Special languages simulation systems for describing the inherent parallel activity in hardware 3 3 03 UCB Spring 2003 CS152 Kubiatowicz Netl ist A key data structure or representation in the design process is the netlist Network List A netlist lists components and connects them with nodes ex n1 n2 n3 n4 g1 n5 g3 g2 n6 g1 and n1 n2 n5 g2 and n3 n4 n6 g3 or n5 n6 n7 n7 Alternative format n1 g1 in1 n2 g1 in2 n3 g2 in1 n4 g2 in2 n5 g1 out g3 in1 n6 g2 out g3 in2 n7 g3 out g1 and g2 and g3 or Netlist is what is needed for simulation and implementation Could be at the transistor level gate level Could be hierarchical or flat How do we generate a netlist 3 3 03 UCB Spring 2003 CS152 Kubiatowicz Des ign Flo w Design Entry Decoder output x0 x1 x2 x3 inputs a b wire abar bbar inv bbar b inv abar a nand x0 abar bbar nand x1 abar b nand x2 a bbar nand x3 a b High level Analysis L o g ic B lo c k Technology Mapping la t c h s e t b y c o n f ig u r a t i o n b it s tr e a m 1 IN P U T S 4 L U T FF OUTPUT 0 4 in p u t lo o k u p ta b le XilinxT Low level Analysis 3 3 03 M UCB Spring 2003 CS152 Kubiatowicz Des ign Flo w Design Entry High level Analysis Circuit is described and represented Graphically Schematics Textually HDL Other Special Compilers Memories Error Correcting Circuite Result of circuit specification and compilation is a netlist of Technology Mapping generic primitives logic gates flip flops or technology specific primitives LUTs CLBs transistors discrete gates or higher level library elements adders ALUs register files decoders etc Low level Analysis 3 3 03 UCB Spring 2003 CS152 Kubiatowicz Des ign Flo w Design Entry High level Analysis High level Analysis is used to verify correct function rough timing power cost Common tools used are Technology Mapping simulator check functional correctness and static timing analyzer estimates circuit delays based on timing model and delay parameters for library elements or primitives Low level Analysis
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