CS152Computer Architecture and EngineeringLecture 2Review of MIPS ISA and Design ConceptsJanuary 26, 2004John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.2Review: OrganizationControlDatapathMemoryProcessorInputOutputAll computers consist of five components•Processor: (1) datapath and (2) control•(3) Memory•I/O: (4) Input devices and (5) Output devicesDatapath and Control typically on on chip1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.3The Instruction Set: a Critical Interfaceinstruction setsoftwarehardware1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.4ISAChoices1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.5Data TypesBit: 0, 1Bit String: sequence of bits of a particular length4 bits is a nibble8 bits is a byte16 bits is a half-word32 bits is a word64 bits is a double-wordCharacter:ASCII 7 bit codeUNICODE 16 bit codeDecimal:digits 0-9 encoded as 0000b thru 1001btwo decimal digits packed per 8 bit byteIntegers:2's ComplementFloating Point:Single PrecisionDouble PrecisionExtended PrecisionM x REHow many +/- #'s?Where is decimal pt?How are +/- exponentsrepresented?exponentbasemantissa1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.6Instruction Set Architecture: What Must be Specified?InstructionFetchInstructionDecodeOperandFetchExecuteResultStoreNextInstructionInstruction Format or Encoding•how is it decoded?Location of operands and result•where other than memory?•how many explicit operands?•how are memory operands located?•which can or cannot be in memory?Data type and SizeOperations•what are supportedSuccessor instruction•jumps, conditions, branches•fetch-decode-execute is implicit!1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.7Top 10 80x86 InstructionsRank instruction Integer Average Percent total executed1 load 22%2 conditional branch 20%3 compare 16%4 store 12%5 add 8%6 and 6%7 sub 5%8 move register-register 4%9 call 1%10 return 1%Total 96%Simple instructions dominate instruction frequency1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.8Operation SummarySupport these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.9Methods of Testing ConditionCondition CodesProcessor status bits are set as a side-effect of arithmetic instructions (possibly on Moves) or explicitly by compare or test instructions.ex: add r1, r2, r3bz labelCondition RegisterEx: cmp r1, r2, r3bgt r1, labelCompare and BranchEx: bgt r1, r2, labelBranches will be the bane of our existence in the future!1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.10Memory AddressingMemory:Continuous LinearAddress Space?ProcessorSince 1980 almost every machine uses addresses to level of 8-bits (byte)2 questions for design of ISA:•How do byte addresses map onto words?•Can a word be placed on any byte boundary?•1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.11Addressing Objects: Endianess and AlignmentBig Endian: address of most significant byte = word address (xx00 = Big End of word)•IBM 360/370, Motorola 68k, MIPS, Sparc, HP PALittle Endian:address of least significant byte = word address(xx00 = Little End of word)•Intel 80x86, DEC Vax, DEC Alpha (Windows NT)little endian byte 03 2 1 0lsbmsb0 1 2 30 1 2 3Alignedbig endian byte 0Alignment: require that objects fall on address that is multiple of their size.NotAligned1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.12Addressing ModesMeaningAddressing mode Example R4← R4+R3Register Add R4,R3R4 ← R4+3Immediate Add R4,#3R4 ← R4+Mem[100+R1]Displacement Add R4,100(R1)R4 ← R4+Mem[R1]Register indirect Add R4,(R1)Add R3,(R1+R2)R3 Indexed / Base← R3+Mem[R1+R2]R1 ← R1+Mem[1001]Direct or absolute Add R1,(1001)R1 ← R1+Mem[Mem[R3]]Memory indirect Add R1,@(R3)R1 ← R1+Mem[R2]; R2 Post-increment Add R1,(R2)+ ← R2+dR2 ← R2–d; R1 Pre-decrement Add R1,–(R2)← R1+Mem[R2]Scaled Add R1,100(R2)[R3]R1 ←R1+Mem[100+R2+R3*d]Why Post-increment/Pre-decrement? Scaled?1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.13Addressing Mode Usage? 3 programs measured on machine with all address modes (VAX)--- Displacement: 42% avg, 32% to 55% 75%--- Immediate: 33% avg, 17% to 43% 85%--- Register deferred (indirect): 13% avg, 3% to 24%--- Scaled: 7% avg, 0% to 16%--- Memory indirect: 3% avg, 1% to 6%--- Misc: 2% avg, 0% to 3%75% displacement & immediate85% displacement, immediate & register indirect1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.14MIPS IInstruction set1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.15MIPS R3000 Instruction Set Architecture (Summary)Register Set•32 general 32-bit registers•Register zero ($R0) always zero•Hi/Lo for multiplication/divisionInstruction Categories•Load/Store•Computational-Integer/Floating point•Jump and Branch•Memory Management•Special3 Instruction Formats: all 32 bits wideR0 - R31RegistersHIPCLOOP rsrtrd sa functOPrsrtimmediatejump targetOP1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.16MIPS Addressing Modes/Instruction Formats•All instructions 32 bits wideopRegister (direct)rs rt rdregisteropimmedImmediaters rtBase+indexopimmedrs rtregister+MemoryPC-relativeopimmedrs rtPC+Memory•Register Indirect?1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.17MIPS I Operation OverviewArithmetic Logical:•Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU•AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI•SLL, SRL, SRA, SLLV, SRLV, SRAVMemory Access:•LB, LBU, LH, LHU, LW, LWL,LWR•SB, SH, SW, SWL, SWR1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.18Multiply / DivideStart multiply, divide•MULT rs, rt•MULTU rs, rt•DIV rs, rt•DIVU rs, rtMove result from multiply, divide•MFHI rd•MFLO rdMove to HI or LO•MTHI rd•MTLO rdWhy not Third field for destination? (Hint: how many clock cycles for multiply or divide vs. add?)RegistersHI LO1/26/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec2.19MIPS arithmetic instructionsInstruction Example Meaning Commentsadd add $1,$2,$3 $1 = $2 + $3 3 operands; exception possiblesubtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possibleadd immediate addi
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