Review Organization Processor Input CS152 Computer Architecture and Engineering Lecture 2 Control Review of MIPS ISA and Design Concepts Datapath Memory Output January 26 2004 John Kubiatowicz http cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 All computers consist of five components Processor 1 datapath and 2 control 3 Memory I O 4 Input devices and 5 Output devices Datapath and Control typically on on chip 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 2 The Instruction Set a Critical Interface software instruction set ISA Choices hardware 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 3 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 4 Instruction Set Architecture What Must be Specified Data Types Bit 0 1 Instruction Bit String sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half word 32 bits is a word 64 bits is a double word Fetch Instruction Decode Character ASCII 7 bit code UNICODE 16 bit code Operand Decimal digits 0 9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Execute Result Store Floating Point exponent How many s Where is decimal pt Single Precision E MxR How are exponents Double Precision represented base Extended Precision CS152 Kubiatowicz mantissa UCB Spring 2004 1 26 03 Lec2 5 Top 10 80x86 Instructions how are memory operands located which can or cannot be in memory Data type and Size Operations what are supported Successor instruction jumps conditions branches Next fetch decode execute is implicit Instruction 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 6 Operation Summary Support these simple instructions since they will dominate the number of instructions executed Integer Average Percent total executed 1 load 22 2 conditional branch 20 3 compare 16 4 store 12 5 add 8 6 and 6 7 sub 5 8 move register register 4 9 call 1 10 return 1 Total 96 load store add subtract move register register and shift compare equal compare not equal branch jump call return Simple instructions dominate instruction frequency 1 26 03 how is it decoded Location of operands and result where other than memory how many explicit operands Fetch Integers 2 s Complement Rank instruction Instruction Format or Encoding UCB Spring 2004 CS152 Kubiatowicz Lec2 7 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 8 Methods of Testing Condition Memory Addressing Condition Codes Processor status bits are set as a side effect of arithmetic instructions possibly on Moves or explicitly by compare or test instructions ex Memory Continuous Linear Address Space Processor add r1 r2 r3 bz label Condition Register Ex cmp r1 r2 r3 Since 1980 almost every machine uses addresses to level of 8 bits byte bgt r1 label Compare and Branch Ex 2 questions for design of ISA bgt r1 r2 label How do byte addresses map onto words Can a word be placed on any byte boundary Branches will be the bane of our existence in the future 1 26 03 CS152 Kubiatowicz Lec2 9 UCB Spring 2004 Addressing Objects Endianess and Alignment 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 10 Addressing Modes Addressing mode Example Meaning Register Add R4 R3 R4 R4 R3 Immediate Add R4 3 R4 R4 3 Displacement Add R4 100 R1 R4 R4 Mem 100 R1 Register indirect Add R4 R1 Indexed Base Add R3 R1 R2 R3 R3 Mem R1 R2 Direct or absolute Add R1 1001 R1 R1 Mem 1001 Memory indirect Add R1 R3 R1 R1 Mem Mem R3 Aligned Post increment Add R1 R2 R1 R1 Mem R2 R2 R2 d Alignment require that objects fall on address that is multiple of their size Not Pre decrement Add R1 R2 R2 R2 d R1 R1 Mem R2 Big Endian address of most significant byte word address xx00 Big End of word IBM 360 370 Motorola 68k MIPS Sparc HP PA Little Endian address of least significant byte word address xx00 Little End of word Intel 80x86 DEC Vax DEC Alpha Windows NT little endian byte 0 3 2 1 0 lsb msb 0 0 big endian byte 0 1 2 1 2 3 3 Scaled Aligned 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 11 Add R1 100 R2 R3 R4 R4 Mem R1 R1 R1 Mem 100 R2 R3 d Why Post increment Pre decrement Scaled 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 12 Addressing Mode Usage 3 programs measured on machine with all address modes VAX Displacement 42 avg 32 to 55 Immediate 33 avg 17 to 43 75 85 Register deferred indirect 13 avg 3 to 24 Scaled 7 avg 0 to 16 Memory indirect 3 avg 1 to 6 Misc 2 avg 0 to 3 MIPS I Instruction set 75 displacement immediate 85 displacement immediate register indirect 1 26 03 CS152 Kubiatowicz Lec2 13 UCB Spring 2004 MIPS R3000 Instruction Set Architecture Summary Register Set 32 general 32 bit registers Register zero R0 always zero Hi Lo for multiplication division Instruction Categories Load Store Computational Integer Floating point Jump and Branch Memory Management Special 3 Instruction Formats all 32 bits wide OP rs rt OP rs rt OP 1 26 03 rd 1 26 03 MIPS Addressing Modes Instruction Formats All instructions 32 bits wide Registers Register direct R0 R31 op rs rt rd register Immediate PC HI Base index LO op rs rt immed op rs rt immed register PC relative sa op rs rt Memory immed Memory funct PC immediate Register Indirect jump target UCB Spring 2004 CS152 Kubiatowicz Lec2 14 UCB Spring 2004 CS152 Kubiatowicz Lec2 15 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 16 MIPS I Operation Overview Multiply Divide Arithmetic Logical Start multiply divide Add AddU Sub SubU And Or Xor Nor SLT SLTU MULT rs rt MULTU rs rt DIV rs rt AddI AddIU SLTI SLTIU AndI OrI XorI LUI SLL SRL SRA SLLV SRLV SRAV Memory Access Registers DIVU rs rt LB LBU LH LHU LW LWL LWR Move result from multiply divide MFHI rd MFLO rd SB SH SW SWL SWR Move to HI or LO HI MTHI rd LO MTLO rd Why not Third field for destination Hint how many clock cycles for multiply or divide vs add 1 26 03 UCB Spring 2004 CS152 Kubiatowicz Lec2 17 Comments 3 operands exception possible 3 operands exception possible constant exception possible 3 operands no exceptions 3 operands no exceptions 1 2 100 constant no except 64 bit signed product 64 bit unsigned product Lo quotient Hi remainder Unsigned quotient remainder Used to get copy of Hi Used to get copy of Lo Instruction Example Meaning and and 1 2 3 1 2 3 3 reg operands Logical AND or or 1 2 3 1 2 3 3 reg operands Logical OR xor xor 1 2 3 1 2 3 3 reg operands Logical XOR nor nor 1 2 3 1 2 3 3 reg operands Logical NOR and immediate andi 1 2 10 1 2 10 Logical AND reg constant or immediate ori 1 2 10 Logical OR reg constant 1 2 10 …
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