CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2005 © UCB2005-9-6John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 3 – Single Cycle Wrap-Upwww-inst.eecs.berkeley.edu/~cs152/TAs: David Marquardt and Udam SainiUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-upLast Time: Goal #1, an R-format CPUopcode rs rt rd functshamtSyntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10Sample program:ADD $8 $9 $10SUB $4 $8 $3AND $9 $8 $4...How registers get their initial values are not of concern to us right now.No loads or stores: machine has no use for data memory, only instruction memory.No branches or jumps: machine only runs straight line code.UC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up Last Time: An R-format CPU design32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opopcode rs rt rd functshamtDecode fields to get : ADD $8 $9 $10 LogicUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up Reminder: How data flows after posedge32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opLogicAddr DataInstrMemDPCQ+0x4UC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up Next posedge: Update state and repeat32rd1RegFile32rd2WE32wd5rs15rs25wsDPCQUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-upToday’s Lecture: Single-Cycle Wrap-upDesign stand-alone machines for other major classes of instructions:immediate ALU, branches, load/store.Implementing control structures for the single-cycle datapath.Learn how to efficiently “merge” single-function machines to make one general-purpose machine.And also, Design Notebook for Lab 2 ...UC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-upGoal #2: add I-format ALU instructionsSyntax: ORI $8 $9 64 Semantics: $8 = $9 | 6416-bit immediate extended to 32 bits.In this example, $9 is rs and $8 is rt. Zero-extend: 0x8000 ⇨0x00008000Sign-extend: 0x8000 ⇨0xFFFF8000Some MIPS instructions zero-extend immediate field, other instructions sign-extend.CS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up Computing engine of the I-format CPU32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opDecode fields to get : ORI $8 $9 64 LogicIn a Verilog implementation, what should we do with rs2?CS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsExtUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opopcode rs rt rd functshamtLogic32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opLogicCS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsExtMerging data paths ...I-formatR-format32MUX3232Add muxesHow many ?Where ?UC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up The merged data path ...32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opopcode rs rt rd functshamtCS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsRegDestALUsrcExtExtOpALUctrUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-upAdministrivia: Upcoming deadlines ...Friday: “Design Document Review” in section, 125 Cory. For non-150s, 150 Lab Lecture, 2-3 PM, 125 Cory.Thursday: Lab 2 preliminary design document due to TAs via email,11:59 PM.Monday: Lab 2 final design document due to TAs via email, 11:59 PM.Tonight: Lab 1 final report due, 11:59 PM, via the submit program.Or email to lazzaro@eecsCS 152 L3: Single Cycle Wrap-up UC Regents Fall 2005 © UCBMemory InstructionsUC Regents Fall 2005 © UCBCS 152 L3: Single Cycle Wrap-up Loads, Stores, and Data Memory ...32DoutData MemoryWE32Din32AddrSyntax: LW $1, 32($2) Syntax: SW $3, 12($4) Action: $1 = M[$2 + 32] Action: M[$4 + 12] = $3CS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsZero-extend or sign-extend immediate field?Writes are clocked: If WE is high, memory Addr captures Din on positive edge of clock.Reads are combinational: Put a stable address on Addr,a short time later Dout is readyNote: Not a realistic main memory (DRAM) model ...CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2005 © UCB Adding data memory to the data path32rd1RegFile32rd2WE32wd5rs15rs25wsCS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt°
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