CS 152 Computer Architecture and Engineering Lecture 2 Single Cycle Datapaths 2005 1 20 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Single cycle CPU project 3 weeks Pipelined CPU 4 weeks Final Project 5 weeks 200 hr student IBM Power 5 die photo a die is an unpackaged part CS 152 L2 Single Cycle Datapaths supports a 1 875 Mbyte on chip L2 cache Power4 and Power4 systems both have 32Mbyte L3 caches whereas Power5 systems have a 36 Mbyte L3 cache Figure 2 Power5 chip FXU fixed point execution unit ISU instruction sequencing unit IDU instruction decode unit LSU load store unit IFU instruction fetch unit FPU floating point unit and MC memory controller W supp threa Proc ing uses T Pow two i two l the c tipro cores cach iden each with The slice can i W chip Havi the p L2 m To r the inate nal c Last Time CS 152 Course Introduction Teams of 4 5 students UC Regents Spring 2005 UCB Today Single Cycle Datapath Design The book presentation of single cycle processors is sufficient to do Lab 2 This lecture is not This lecture is a gentle introduction to prepare you to read the book CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Single cycle data paths Assumptions Processor uses synchronous logic design a clock 0 7 4 f 1 MHz 10 MHz T 1 s 100 ns 100 MHz 10 ns 1 GHz 1 ns D All state elements act like positive edgetriggered flip flops Q 5 5 0 0 clk CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Review Edge Triggered D Flip Flops D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle CLK D Q CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Review Edge Triggering in Verilog D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle module ff D Q CLK CLK input D CLK output Q always CLK Q D Module code has two bugs Where endmodule CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Review Edge Triggered D Flip Flops D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle module ff D Q CLK CLK input D CLK output Q reg Q Correct always posedge CLK Q D endmodule CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Administrivia Upcoming deadlines Friday Teams meet the TAs 12 1 119 Cory For 61 c students 150 Lab Lecture 1 1 2 PM 125 Cory Monday Lab 1 final report due 11 59 PM via the submit program Thursday Lab 2 preliminary design document due to TAs via email 11 59 PM CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Single cycle data paths Definition 0 7 4 All instructions execute in a single cycle of the clock positive edge to 5 60 7 89 positive edge 5 0 7 8 Advantage a great way to learn CPUs CS 152 L2 Single Cycle Datapaths Drawbacks unrealistic 012 34 5 hardware assumptions slow clock period UC Regents Spring 2005 UCB Recall MIPS R format instructions Syntax ADD 8 9 10 Semantics 8 9 10 Instruction Fetch Fetch next inst from memory 012A4020 Instruction Decode opcode rs rt rd shamt funct Decode fields to get ADD 8 9 10 Operand Fetch Execute Result Store Next Instruction Retrieve register values 9 10 Add 9 to 10 Place this sum in 8 Prepare to fetch instruction that follows the ADD in the program CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Goal 1 An R format single cycle CPU Syntax ADD 8 9 10 opcode Sample ADD 8 SUB 4 AND 9 rs program 9 10 8 3 8 4 How registers get their initial values are not of concern to us right now CS 152 L2 Single Cycle Datapaths rt Semantics 8 9 10 rd shamt funct No branches or jumps machine only runs straight line code No loads or stores machine has no use for data memory only instruction memory UC Regents Spring 2005 UCB Separate Read Only Instruction Memory Instr Mem 32 Data Reads are combinational Put a stable address on input a short time later data appears on output Addr 32 Not concerned about how programs are loaded into this memory CS 152 L2 Single Cycle Datapaths Related to separate instruction and data caches in real designs UC Regents Spring 2005 UCB Task 1 Straight line Instruction Fetch R Instr Mem 32 Data eq Fetching straight line MIPS u i rem instructions requires a machine ents that generates this timing diagram Why do we increment every clock cycle Why 4 and not 1 Addr 32 CLK Addr Data PC PC 4 IMem PC IMem PC 4 PC 8 IMem PC 8 PC Program Counter points to next instruction CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB New Component Register for PC Built out of an array of flip flops Din0 D Q Dout0 Din1 D Q Dout1 Din2 D Q Dout2 PC 32 32 Din Dout Clk In later examples we will add an enable input clock edge updates state only if enable is high clk CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB New Component A 32 bit adder ALU 32 A 32 A B 32 B op 32 ln ops 32 A L U A B 32 A op B Zero Combinational Put a A and B values on inputs a short time later A B appears on output ALU Combinational part that is able to execute many functions of A and B add sub and or The op value selects the function Sometimes extra outputs for use by control logic CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Design Straight line Instruction Fetch CS 152 State machine design in the service of an ISA 32 PC Instr Mem 32 32 32 D Q 32 Addr Data 32 0x4 4 in hexadecimal Clk CLK Addr PC Data CS 152 L2 Single Cycle Datapaths PC 4 IMem PC IMem PC 4 PC 8 IMem PC 8 UC Regents Spring 2005 UCB Goal 1 An R format single cycle CPU Syntax ADD 8 9 10 Semantics 8 9 10 Done To continue we need registers Instruction Fetch Fetch next inst from memory 012A4020 Instruction Decode opcode rs rt rd shamt funct Decode fields to get ADD 8 9 10 Operand Fetch Execute Result Store Next Instruction Retrieve register values 9 10 Add 9 to 10 Place this sum in 8 Prepare to fetch instruction that follows the ADD in the program CS 152 L2 Single Cycle Datapaths UC Regents Spring 2005 UCB Register files From the top down clk sel ws 5 Why is R0 special R0 The constant 0 D D E WE M U …
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