CS152 Computer Architecture and Engineering Lecture 14 Pipelining Control Continued Introduction to Advanced Pipelining October 19 2001 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Recap Summary of Pipelining Basics 5 stages Fetch Fetch instruction from memory Decode get register values and decode control information Execute Execute arithmetic operations calculate addresses Memory Do memory ops load or store Writeback Write results back to registers I e COMMIT Pipelines pass control information down the pipe just as data moves down pipe Forwarding Stalls handled by local control Balancing length of instructions makes pipelining much smoother Increasing length of pipe increases impact of hazards pipelining helps instruction bandwidth not latency 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Recap Can pipelining get us into trouble Yes Pipeline Hazards structural hazards attempt to use the same resource two different ways at the same time E g combined washer dryer would be a structural hazard or folder busy doing something else watching TV data hazards attempt to use item before it is ready E g one sock of pair in dryer and one in washer can t fold until get sock from washer through dryer instruction depends on result of prior instruction still in the pipeline control hazards attempt to make a decision before condition is evaulated E g washing football uniforms and need to get proper detergent level need to see after dryer before next load in branch instructions Can always resolve hazards by waiting 10 19 01 pipeline control must detect the hazard take action or delay action to resolve hazards UCB Fall 2001 CS152 Kubiatowicz Pipelining the Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Clock 1st lw Ifetch Reg Dec 2nd lw Ifetch 3rd lw Exec Mem Wr Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr The five independent functional units in the pipeline datapath are Instruction Memory for the Ifetch stage Register File s Read ports bus A and busB for the Reg Dec stage ALU for the Exec stage Data Memory for the Mem stage Register File s Write port bus W for the Wr stage 10 19 01 UCB Fall 2001 CS152 Kubiatowicz The Four Stages of Rtype Cycle 1 Cycle 2 Cycle 3 R type Ifetch Reg Dec Exec Cycle 4 Wr Ifetch Instruction Fetch Fetch the instruction from the Instruction Memory Reg Dec Registers Fetch and Instruction Decode Exec ALU operates on the two register operands Update PC Wr Write the ALU output back to the register file 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Pipelining the R type and Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R type Ifetch R type Reg Dec Exec Ifetch Reg Dec Exec Ifetch Reg Dec Load Ops We have a problem Wr R type Ifetch Wr Exec Mem Wr Reg Dec Exec Wr R type Ifetch Reg Dec Exec Wr We have pipeline conflict or structural hazard Two instructions try to write to the register file at the same time Only one write port 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Important Observation Each functional unit can only be used once per instruction Each functional unit must be used at the same stage for all instructions Load uses Register File s Write Port during its 5th stage Load 1 2 3 Ifetch Reg Dec Exec 4 5 Mem Wr R type uses Register File s Write Port during its 4th stage 1 R type Ifetch 2 Reg Dec 3 Exec 4 Wr 2 ways to solve this pipeline hazard 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Solution 1 Insert Bubble into the Pipeline Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock Ifetch Load Reg Dec Exec Ifetch Reg Dec R type Ifetch Wr Exec Mem Reg Dec Exec Wr Wr R type Ifetch Reg Dec Pipeline Exec R type Ifetch Bubble Reg Dec Ifetch Wr Exec Reg Dec Wr Exec Insert a bubble into the pipeline to prevent 2 writes at the same cycle The control logic can be complex Lose instruction fetch and issue opportunity No instruction is started in Cycle 6 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Solution 2 Delay R type s Write by One Cycle Delay R type s register write by one cycle Now R type instructions also use Reg File s write port at Stage 5 Mem stage is a NOOP stage nothing is being done 1 2 R type Ifetch Cycle 1 Cycle 2 Reg Dec 3 Exec 4 Mem 5 Wr Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R type Ifetch R type Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr Reg Dec Exec Mem Wr Reg Dec Exec Mem Load R type Ifetch R type Ifetch 10 19 01 UCB Fall 2001 Wr CS152 Kubiatowicz Modified Control Datapath IR Mem PC PC PC 4 A R rs B R rt S A SX M S M Mem S Mem S B Data Mem B UCB Fall 2001 Reg File M S D 10 19 01 if Cond PC PC SX Mem Access A Exec R rd M IR Inst Mem R rt M PC Next PC R rd M S A SX Equal M S S A or ZX Reg File S A B CS152 Kubiatowicz The Four Stages of Store Cycle 1 Cycle 2 Store Ifetch Reg Dec Cycle 3 Cycle 4 Exec Mem Wr Ifetch Instruction Fetch Fetch the instruction from the Instruction Memory Reg Dec Registers Fetch and Instruction Decode Exec Calculate the memory address Mem Write the data into the Data Memory 10 19 01 UCB Fall 2001 CS152 Kubiatowicz The Three Stages of Beq Cycle 1 Cycle 2 Beq Ifetch Reg Dec Cycle 3 Cycle 4 Exec Mem Wr Ifetch Instruction Fetch Fetch the instruction from the Instruction Memory Reg Dec Registers Fetch and Instruction Decode Exec compares the two register operand select correct branch target address latch into PC 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Control Diagram IR Mem PC PC PC 4 A R rs B R rt S A SX M S M Mem S Mem S B Data Mem B UCB Fall 2001 Reg File M S D 10 19 01 If Cond PC PC SX Mem Access A Exec R rd M IR Inst Mem R rt S PC Next PC R rd S S A SX Equal M S S A or ZX Reg File S A B CS152 Kubiatowicz Administrivi a Updated Lab 5 schedule Up there now sorry about that Mail problem 0 to TA by Monday night at Midnight Evaluation of your partners Mail Lab 5 breakdowns to your TAs by Wednesday at Midnight Get started on Lab 5 Pipelining is difficult to get right Be sure that we will test gotcha cases in our mystery programs We are …
View Full Document
Unlocking...