CS 152 Computer Architecture and Engineering Lecture 11 Out of Order Issue Register Renaming Branch Prediction Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 March 2 2011 CS152 Spring 2011 Last time in Lecture 12 Pipelining is complicated by multiple and or variable latency functional units Out of order and or pipelined execution requires tracking of dependencies RAW WAR WAW Dynamic issue logic can support out of order execution to improve performance Last time looked at simple scoreboard to track out of order completion Hardware register renaming can further improve performance by removing hazards March 2 2011 CS152 Spring 2011 2 Register Renaming ALU IF ID Mem Issue WB Fadd Fmul Decode does register renaming and adds instructions to the issue stage instruction reorder buffer ROB renaming makes WAR or WAW hazards impossible Any instruction in ROB whose RAW hazards have been satisfied can be dispatched Out of order or dataflow execution March 2 2011 CS152 Spring 2011 3 Renaming Structures Renaming table regfile Ins use exec op p1 src1 p2 src2 Reorder buffer Replacing the tag by its value is an expensive operation Load Unit FU FU t1 t2 tn Store Unit t result Instruction template i e tag t is allocated by the Decode stage which also associates tag with register in regfile When an instruction completes its tag is deallocated March 2 2011 CS152 Spring 2011 4 Reorder Buffer Management Ins use exec op p1 src1 p2 src2 t1 t2 Destination registers are renamed to the ptr2 next to deallocate instruction s slot tag ptr1 next available tn ROB managed circularly exec bit is set when instruction begins execution When an instruction completes its use bit is marked free ptr2 is incremented only if the use bit is marked free Instruction slot is candidate for execution when It holds a valid instruction use bit is set It has not already started execution exec bit is clear Both operands are available p1 and p2 are set March 2 2011 CS152 Spring 2011 5 Renaming Out of order Issue An example Renaming table p v1 F1 F2 F3 F4 F5 F6 F7 F8 data v1 t1 t5 t2 Reorder buffer Ins use exec op p1 src1 p2 src2 0 1 1 0 LD LD 3 0 1 10 1 0 MUL 10 v2 t2 11 v1 v1 4 5 10 1 1 0 0 SUB DIV 1 1 v1 v1 1 0 1 v1 t4 v4 1 22 t3 t1 t2 t3 t4 t5 v4 t4 data ti 1 2 3 4 5 6 LD LD MULTD SUBD DIVD ADDD March 2 2011 F2 F4 F6 F8 F4 F10 34 R2 45 R3 F4 F2 F2 F6 F2 F2 F8 F4 When are tags in sources replaced by data Whenever an FU produces data When can a name be reused Whenever an instruction completes CS152 Spring 2011 6 IBM 360 91 Floating Point Unit R M Tomasulo 1967 1 2 3 4 5 6 p p p p p p Distribute instruction templates by functional units tag data tag data tag data tag data tag data tag data load buffers from memory instructions 1 2 3 4 p p p p tag data tag data tag data tag data FloatingPoint Regfile 1 p tag data p tag data 2 p tag data p tag data 1 p tag data p tag data 3 p tag data p tag data 2 p tag data p tag data Adder Mult tag result store buffers to memory March 2 2011 p tag data p tag data p tag data Common bus ensures that data is made available immediately to all the instructions waiting for it Match tag if equal copy value set presence p CS152 Spring 2011 7 Effectiveness Renaming and Out of order execution was first implemented in 1969 in IBM 360 91 but did not show up in the subsequent models until midNineties Why Reasons 1 Effective on a very small class of programs 2 Memory latency a much bigger problem 3 Exceptions not precise One more problem needed to be solved Control Hazards March 2 2011 CS152 Spring 2011 8 Precise Interrupts It must appear as if an interrupt is taken between two instructions say Ii and Ii 1 the effect of all instructions up to and including Ii is totally complete no effect of any instruction after Ii has taken place The interrupt handler either aborts the program or restarts it at Ii 1 March 2 2011 CS152 Spring 2011 9 Effect on Interrupts Out of order Completion I1 I2 I3 I4 I5 I6 out of order comp DIVD LD MULTD DIVD SUBD ADDD 1 2 f6 f2 f0 f8 f10 f6 2 3 f6 45 r3 f2 f6 f0 f8 1 4 3 5 restore f2 f4 f4 f2 f6 f2 5 4 6 6 restore f10 Consider interrupts Precise interrupts are difficult to implement at high speed want to start execution of later instructions before exception checks finished on earlier instructions March 2 2011 CS152 Spring 2011 10 Exception Handling Commit Point In Order Five Stage Pipeline Inst Mem PC Select Handler PC PC Address Exceptions Kill F Stage D Decode E Illegal Opcode M Overflow Data Mem Data Addr Except W Kill Writeback Exc D Exc E Exc M Cause PC D PC E PC M EPC Kill D Stage Kill E Stage Asynchronous Interrupts Hold exception flags in pipeline until commit point M stage Exceptions in earlier pipe stages override later exceptions Inject external interrupts at commit point override others If exception at commit update Cause and EPC registers kill all stages inject handler PC into fetch stage March 2 2011 CS152 Spring 2011 11 Phases of Instruction Execution PC I cache Fetch Instruction bits retrieved from cache Fetch Buffer Decode Rename Decode Instructions dispatched to appropriate issue stage buffer Issue Buffer Execute Instructions and operands issued to execution units Functional Units When execution completes all results and exception flags are available Result Buffer Commit Commit Instruction irrevocably updates architectural state aka graduation Architectural State March 2 2011 CS152 Spring 2011 12 In Order Commit for Precise Exceptions In order Fetch Out of order Reorder Buffer Decode Kill In order Commit Kill Kill Execute Inject handler PC Exception Instructions fetched and decoded into instruction reorder buffer in order Execution is out of order out of order completion Commit write back to architectural state i e regfile memory is in order Temporary storage needed to hold results before commit shadow registers and store buffers March 2 2011 CS152 Spring 2011 13 Extensions for Precise Exceptions Inst use exec op p1 src1 p2 src2 pd dest data cause ptr2 next to commit ptr1 next available Reorder buffer add pd dest data cause fields in the instruction template commit instructions to reg file and memory in program order buffers can be maintained circularly on exception clear reorder buffer by resetting ptr1 ptr2 stores must wait for commit before updating memory March 2 2011 CS152 Spring 2011 14 Rollback and Renaming Register File now holds only committed
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