March 2, 2011 CS152, Spring 2011 CS 152 Computer Architecture and Engineering Lecture 11 - Out-of-Order Issue, Register Renaming, & Branch Prediction Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!http://inst.eecs.berkeley.edu/~cs152!March 2, 2011 CS152, Spring 2011 2 Last time in Lecture 12 • Pipelining is complicated by multiple and/or variable latency functional units • Out-of-order and/or pipelined execution requires tracking of dependencies – RAW – WAR – WAW • Dynamic issue logic can support out-of-order execution to improve performance – Last time, looked at simple scoreboard to track out-of-order completion • Hardware register renaming can further improve performance by removing hazards.March 2, 2011 CS152, Spring 2011 3 Register Renaming • Decode does register renaming and adds instructions to the issue-stage instruction reorder buffer (ROB) ⇒ renaming makes WAR or WAW hazards impossible • Any instruction in ROB whose RAW hazards have been satisfied can be dispatched. " "⇒ Out-of-order or dataflow execution IF ID WB ALU Mem Fadd Fmul IssueMarch 2, 2011 CS152, Spring 2011 4 Renaming Structures Renaming table & regfile Reorder buffer Load Unit FU FU Store Unit < t, result > Ins# use exec op p1 src1 p2 src2 t1 t2 . . tn • Instruction template (i.e., tag t) is allocated by the Decode stage, which also associates tag with register in regfile • When an instruction completes, its tag is deallocated Replacing the tag by its value is an expensive operationMarch 2, 2011 CS152, Spring 2011 5 Reorder Buffer Management Instruction slot is candidate for execution when: • It holds a valid instruction (“use” bit is set) • It has not already started execution (“exec” bit is clear) • Both operands are available (p1 and p2 are set) t1 t2 . . . tn ptr2 next to deallocate ptr1 next available Ins# use exec op p1 src1 p2 src2 Destination registers are renamed to the instruction’s slot tag ROB managed circularly • “exec” bit is set when instruction begins execution • When an instruction completes its “use” bit is marked free • ptr2 is incremented only if the “use” bit is marked freeMarch 2, 2011 CS152, Spring 2011 6 Renaming & Out-of-order Issue An example • When are tags in sources replaced by data? • When can a name be reused? 1 LD F2, 34(R2) 2 LD F4, 45(R3) 3 MULTD F6, F4, F2 4 SUBD F8, F2, F2 5 DIVD F4, F2, F8 6 ADDD F10, F6, F4 Renaming table Reorder buffer Ins# use exec op p1 src1 p2 src2 t1 t2 t3 t4 t5 . . data / ti p data F1 F2 F3 F4 F5 F6 F7 F8 Whenever an FU produces data Whenever an instruction completes t1 1 1 0 LD t2 2 1 0 LD 5 1 0 DIV 1 v1 0 t4 4 1 0 SUB 1 v1 1 v1 t4 3 1 0 MUL 0 t2 1 v1 t3 t5 v1 v1 1 1 1 LD 0 4 1 1 SUB 1 v1 1 v1 4 0 v4 5 1 0 DIV 1 v1 1 v4 2 1 1 LD 2 0 3 1 0 MUL 1 v2 1 v1March 2, 2011 CS152, Spring 2011 7 IBM 360/91 Floating-Point Unit R. M. Tomasulo, 1967 Mult 1 1 2 3 4 5 6 load buffers (from memory) 1 2 3 4 Adder 1 2 3 Floating- Point Regfile store buffers (to memory) ... instructions Common bus ensures that data is made available immediately to all the instructions waiting for it. Match tag, if equal, copy value & set presence “p”. Distribute instruction templates by functional units < tag, result > p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data 2 p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/data p tag/dataMarch 2, 2011 CS152, Spring 2011 8 Effectiveness? Renaming and Out-of-order execution was first implemented in 1969 in IBM 360/91 but did not show up in the subsequent models until mid-Nineties. Why ? Reasons 1. Effective on a very small class of programs 2. Memory latency a much bigger problem 3. Exceptions not precise! One more problem needed to be solved Control Hazards!March 2, 2011 CS152, Spring 2011 9 Precise Interrupts It must appear as if an interrupt is taken between two instructions (say Ii and Ii+1) • the effect of all instructions up to and including Ii is totally complete • no effect of any instruction after Ii has taken place The interrupt handler either aborts the program or restarts it at Ii+1 .March 2, 2011 CS152, Spring 2011 10 Effect on Interrupts Out-of-order Completion I1 DIVD f6, f6, f4 I2 LD f2, 45(r3) I3 MULTD f0, f2, f4 I4 DIVD f8, f6, f2 I5 SUBD f10, f0, f6 I6 ADDD f6, f8, f2 out-of-order comp 1 2 2 3 1 4 3 5 5 4 6 6 restore f2 restore f10 Consider interrupts Precise interrupts are difficult to implement at high speed - want to start execution of later instructions before exception checks finished on earlier instructionsMarch 2, 2011 CS152, Spring 2011 11 Exception Handling (In-Order Five-Stage Pipeline) • Hold exception flags in pipeline until commit point (M stage) • Exceptions in earlier pipe stages override later exceptions • Inject external interrupts at commit point (override others) • If exception at commit: update Cause and EPC registers, kill all stages, inject handler PC into fetch stage Asynchronous Interrupts Exc D PC D PC Inst. Mem D Decode E M Data Mem W + Exc E PC E Exc M PC M Cause EPC Kill D Stage Kill F Stage Kill E Stage Illegal Opcode Overflow Data Addr Except PC Address Exceptions Kill Writeback Select Handler PC Commit PointMarch 2, 2011 CS152, Spring 2011 12 Fetch: Instruction bits retrieved from cache. Phases of Instruction Execution I-cache Fetch Buffer Issue Buffer Functional Units Architectural State Execute: Instructions and operands issued to execution units. When execution completes, all results and exception
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