CS152 Computer Architecture and Engineering Lecture 23 I/O and Storage SystemsRecap: A Three-Bus System (+ backside cache)Recap: Main components of Intel Chipset: Pentium II/IIIArbitration: Obtaining Access to the BusThe Daisy Chain Bus Arbitrations SchemeCentralized Parallel ArbitrationIncreasing the Bus BandwidthIncreasing Transaction Rate on Multimaster BusRecall: PCI Read TransactionI/O Device ExamplesI/O System PerformanceSimple Producer-Server ModelThroughput versus Respond TimeThroughput EnhancementOrganization of a Hard Magnetic DiskMagnetic Disk CharacteristicTechnology TrendsDisk HistorySlide 19MBits per square inch: DRAM as % of Disk over timeNano-layered Disk HeadsDisk Device TerminologyTypical Numbers of a Magnetic DiskAdministriviaAdministrivia II: Final project optionsDisk I/O PerformanceIntroduction to Queueing TheoryA Little Queuing Theory: Use of random distributionsA Little Queuing Theory: Variable Service TimeA Little Queuing Theory: Average Wait TimeA Little Queuing Theory: M/G/1 and M/M/1A Little Queuing Theory: An ExampleMemory System I/O PerformanceGiving Commands to I/O DevicesMemory Mapped I/OI/O Device Notifying the OSExample: Device InterruptAlternative: PollingPolling: Programmed I/OPolling is faster/slower than InterruptsDelegating I/O Responsibility from the CPU: DMADelegating I/O Responsibility from the CPU: IOPReliability and AvailabilityManufacturing Advantages of Disk ArraysArray ReliabilityRedundant Arrays of DisksRAID 1: Disk Mirroring/ShadowingRAID 3: Parity DiskRAID 5+: High I/O Rate ParityProblems of Disk Arrays: Small WritesHewlett-Packard (HP) AutoRAIDI/O Summary:CS152Computer Architecture and Engineering Lecture 23I/O and Storage SystemsApril 26, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.2Recap: A Three-Bus System (+ backside cache)°A small number of backplane buses tap into the processor-memory bus•Processor-memory bus is only used for processor-memory traffic•I/O buses are connected to the backplane bus°Advantage: loading on the processor bus is greatly reducedProcessor MemoryProcessor Memory BusBusAdaptorBusAdaptorBusAdaptorI/O BusBacksideCache busI/O BusL2 Cache4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.3Recap: Main components of Intel Chipset: Pentium II/III°Northbridge:•Handles memory•Graphics°Southbridge: I/O•PCI bus•Disk controllers•USB controlers•Audio•Serial I/O•Interrupt controller•Timers4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.4°One of the most important issues in bus design:•How is the bus reserved by a device that wishes to use it?°Chaos is avoided by a master-slave arrangement:•Only the bus master can control access to the bus:It initiates and controls all bus requests•A slave responds to read and write requests°The simplest system:•Processor is the only bus master•All bus requests must be controlled by the processor•Major drawback: the processor is involved in every transactionBusMasterBusSlaveControl: Master initiates requestsData can go either wayArbitration: Obtaining Access to the Bus4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.5The Daisy Chain Bus Arbitrations Scheme°Advantage: simple°Disadvantages:•Cannot assure fairness: A low-priority device may be locked out indefinitely•The use of the daisy chain grant signal also limits the bus speedBusArbiterDevice 1HighestPriorityDevice NLowestPriorityDevice 2Grant Grant GrantReleaseRequestwired-OR4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.6°Used in essentially all processor-memory busses and in high-speed I/O bussesBusArbiterDevice 1Device NDevice 2GrantReqCentralized Parallel Arbitration4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.7°Separate versus multiplexed address and data lines:•Address and data can be transmitted in one bus cycle if separate address and data lines are available•Cost: (a) more bus lines, (b) increased complexity°Data bus width:•By increasing the width of the data bus, transfers of multiple words require fewer bus cycles•Example: SPARCstation 20’s memory bus is 128 bit wide•Cost: more bus lines°Block transfers:•Allow the bus to transfer multiple words in back-to-back bus cycles•Only one address needs to be sent at the beginning•The bus is not released until the last word is transferred•Cost: (a) increased complexity (b) decreased response time for requestIncreasing the Bus Bandwidth4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.8°Overlapped arbitration•perform arbitration for next transaction during current transaction°Bus parking•master can holds onto bus and performs multiple transactions as long as no other master makes request°Overlapped address / data phases (prev. slide)•requires one of the above techniques°Split-phase (or packet switched) bus•completely separate address and data phases•arbitrate separately for each•address phase yield a tag which is matched with data phase°“All of the above” in most modern busesIncreasing Transaction Rate on Multimaster Bus4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.9– Turn-around cycle on any signal driven by more than one agentRecall: PCI Read Transaction4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.10I/O Device ExamplesDevice Behavior Partner Data Rate (KB/sec)Keyboard Input Human 0.01Mouse Input Human 0.02Line Printer Output Human 1.00Floppy disk Storage Machine 50.00Laser Printer Output Human 100.00Optical Disk Storage Machine 500.00Magnetic Disk Storage Machine 5,000.00Network-LAN Input or Output Machine 20 – 1,000.00Graphics Display Output Human 30,000.004/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.11I/O System Performance°I/O System performance depends on many aspects of the system (“limited by weakest link in the chain”):•The CPU•The memory system:-Internal and external caches-Main Memory•The underlying interconnection (buses)•The I/O controller•The I/O device•The speed of the I/O software (Operating System)•The efficiency of the software’s use of the I/O devices°Two common performance metrics:•Throughput: I/O bandwidth•Response time: Latency4/26/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec23.12Simple Producer-Server
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