Today s Outline Review of Last lecture CS152 Computer Architecture and Engineering Lecture 5 Intro to VHDL Administrative Issues VHDL Multiply Shift on line lab notebook Designing a Multiplier Feb 8 1999 Booth s algorithm John Kubiatowicz http cs berkeley edu kubitron Shifters lecture slides http www inst eecs berkeley edu cs152 2 8 99 CS152 Kubiatowicz Lec5 1 UCB Spring 1999 Review ALU Design CS152 Kubiatowicz Lec5 2 Divide and Conquer e g ALU Formulate a solution in terms of simpler components Design each of the components subproblems Overflow means number too large for the representation Carry look ahead and other adder tricks 32 B Generate and Test e g ALU Given a collection of building blocks look for ways of putting them together that meets requirement 32 signed arith and cin xor co a0 a31 b31 b0 ALU0 co cin s0 ALU31 co cin s31 32 Ovflw S 2 8 99 UCB Spring 1999 Review Elements of the Design Process Bit slice plus extra on the two ends A 2 8 99 UCB Spring 1999 Successive Refinement e g multiplier divider Solve most of the problem i e ignore some constraints or special cases examine and correct shortcomings 4 M C L to produce select comp c in CS152 Kubiatowicz Lec5 3 Formulate High Level Alternatives e g shifter Articulate many strategies to keep in mind while pursuing any one approach Work on the Things you Know How to Do The unknown will become obvious as you make progress 2 8 99 UCB Spring 1999 CS152 Kubiatowicz Lec5 4 Review Cost Price and Online Notebook Review Summary of the Design Process Cost and Price Hierarchical Design to manage complexity Die size determines chip cost cost die size 1 Cost v Price business model of company pay for engineers R D must return 8 to 14 for every 1 invester Top Down vs Bottom Up vs Successive Refinement Importance of Design Representations Block Diagrams top down Decomposition into Bit Slices bottom up Truth Tables K Maps On line Design Notebook Open a window and keep an editor running while you work cut paste Refer to the handout as an example Former CS 152 students and TAs say they use on line notebook for programming as well as hardware design one of most valuable skills Circuit Diagrams Other Descriptions state diagrams timing diagrams reg xfer Optimization Criteria Area Gate Count Logic Levels Delay Pin Out 2 8 99 Power Fan in Fan out Package Count Cost Design time UCB Spring 1999 CS152 Kubiatowicz Lec5 5 2 8 99 UCB Spring 1999 CS152 Kubiatowicz Lec5 6 Simulation Before Construction Representation Languages Hardware Representation Languages Physical Breadboarding Block Diagrams FUs Registers Dataflows discrete components lower scale integration preceeds actual construction of prototype Register Transfer Diagrams Choice of busses to connect FUs Regs Flowcharts verify initial design concept Two different ways to describe sequencing microoperations State Diagrams No longer possible as designs reach higher levels of integration Fifth Representation Language Hardware Description Languages hw modules described like programs with i o ports internal state parallel execution of assignment statements E G ISP VHDL Verilog Simulation Before Construction high level constructs implies faster to construct play what if more easily Descriptions in these languages can be used as input to software breadboard synthesis systems generate hw from high level description To Design is to Represent 2 8 99 limited performance accuracy however simulation systems UCB Spring 1999 CS152 Kubiatowicz Lec5 7 2 8 99 UCB Spring 1999 CS152 Kubiatowicz Lec5 8 Levels of Description Architectural Simulation Functional Behavioral Register Transfer Logic VHDL VHSIC Hardware Description Language models programmer s view at a high level written in your favorite programming language more detailed model like the block diagram view Goals Support design documentation and simulation of hardware Less Abstract More Accurate Slower Simulation commitment to datapath FUs registers busses register xfer operations are clock phase accurate Digital system level to gate level Technology Insertion Concepts Design entity Time based execution model model is in terms of logic gates higher level MSI functions described in terms of these Circuit Interface External Characteristics Design Entity Hardware Component electrical behavior accurate waveforms Schematic capture logic simulation package like Powerview Special languages simulation systems for describing the inherent parallel activity in hardware 2 8 99 UCB Spring 1999 CS152 Kubiatowicz Lec5 9 Architecture Body Internal Behavior or Structure 2 8 99 Interface ENTITY nand is PORT a b IN VLBIT y OUT VLBIT END nand ARCHITECTURE behavioral OF nand is BEGIN y a NAND b determined where instantiated or by default END behavioral Internally Visible Characteristics Declarations Assertions constraints on all alternative bodies i e implmentations Architecture 2 8 99 CS152 Kubiatowicz Lec5 10 VHDL Example nand gate Externally Visible Characterisitcs Ports channels of communication inputs outputs clocks control Generic Parameters define class of components timing characterisitcs size fan out Interface UCB Spring 1999 Entity describes interface Architecture give behavior i e function y is a signal not a variable it changes when ever the inputs change drive a signal NAND process is in an infinite loop view to other modules details of implementation UCB Spring 1999 CS152 Kubiatowicz Lec5 11 VLBit is 0 1 X or Z 2 8 99 UCB Spring 1999 CS152 Kubiatowicz Lec5 12 Modeling Delays Generic Parameters ENTITY nand is ENTITY nand is GENERIC delay TIME 1ns PORT a b IN VLBIT y OUT VLBIT PORT a b IN VLBIT y OUT VLBIT END nand END nand ARCHITECTURE behavioral OF nand is ARCHITECTURE behavioral OF nand is BEGIN BEGIN y a NAND b after 1 ns y a NAND b AFTER delay END behavioral END behavioral Model temporal as well as functional behavior with delays in signal statements Time is one difference from programming languages y changes 1 ns after a or b changes This fixed delay is inflexible hard to reflect changes in technology Generic parameters provide default values may be overidden on each instance attach value to symbol as attribute Separate functional and temporal models How would you describe fix delay slope load model 2 8 99 UCB Spring 1999 CS152 Kubiatowicz Lec5 13 2 8 99 Bit vector data type UCB Spring 1999 CS152 Kubiatowicz Lec5 14 Arithmetic Operations ENTITY nand32 is ENTITY add32 is PORT a b IN VLBIT 1D 31 downto 0 PORT a b IN VLBIT 1D 31 downto 0 y OUT VLBIT 1D 31
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