2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.1CS152Computer Architecture and Engineering Lecture 5 VHDL, Multiply, ShiftFeb 8, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.2Today’s Outline° Review of Last lecture° Intro to VHDL° Administrative Issues° on-line lab notebook° Designing a Multiplier° Booth’s algorithm° Shifters2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.3Review: ALU Design° Bit-slice plus extra on the two ends° Overflow means number too large for the representation° Carry-look ahead and other adder tricksAMS32324OvflwALU0a0 b0cincos0ALU31a31 b31cincos31B 32C/L toproduceselect,comp,c-insigned-arithand cin xor co2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.4Review: Elements of the Design Process° Divide and Conquer (e.g., ALU)• Formulate a solution in terms of simpler components.• Design each of the components (subproblems)° Generate and Test (e.g., ALU)• Given a collection of building blocks, look for ways of puttingthem together that meets requirement° Successive Refinement (e.g., multiplier, divider)• Solve "most" of the problem (i.e., ignore some constraints orspecial cases), examine and correct shortcomings.° Formulate High-Level Alternatives (e.g., shifter)• Articulate many strategies to "keep in mind" while pursuing anyone approach.° Work on the Things you Know How to Do• The unknown will become “obvious” as you make progress.2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.5Review: Summary of the Design ProcessHierarchical Design to manage complexityTop Down vs. Bottom Up vs. Successive RefinementImportance of Design Representations: Block Diagrams Decomposition into Bit Slices Truth Tables, K-Maps Circuit Diagrams Other Descriptions: state diagrams, timing diagrams, reg xfer, . . .Optimization Criteria: Gate Count [Package Count]Logic LevelsFan-in/Fan-outPowertopdownbottom upAreaDelayCost Design timePin Out2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.6Review: Cost/Price and Online Notebook° Cost and Price• Die size determines chip cost: cost ≈ die size(α +1)• Cost v. Price: business model of company, pay for engineers• R&D must return $8 to $14 for every $1 invester° On-line Design Notebook• Open a window and keep an editor running while you work;cut&paste• Refer to the handout as an example• Former CS 152 students (and TAs) say they use on-line notebook forprogramming as well as hardware design; one of most valuable skills2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.7Hardware Representation Languages: Block Diagrams: FUs, Registers, & Dataflows Register Transfer Diagrams: Choice of busses to connect FUs, Regs Flowcharts State DiagramsFifth Representation "Language": Hardware Description Languages E.G., ISP’ VHDL VerilogDescriptions in these languages can be used as input to simulation systems synthesis systemsRepresentation LanguagesTwo different ways to describe sequencing & microoperationshw modules described like programswith i/o ports, internal state, & parallelexecution of assignment statements"software breadboard"generate hw from high level description"To Design is to Represent"2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.8Simulation Before Construction"Physical Breadboarding" discrete components/lower scale integration preceeds actual construction of prototype verify initial design conceptNo longer possible as designs reach higher levels of integration!Simulation Before Construction high level constructs implies faster to construct play "what if" more easily limited performance accuracy, however2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.9Levels of DescriptionArchitectural SimulationFunctional/BehavioralRegister TransferLogicCircuitmodels programmer’s view at ahigh level; written in your favoriteprogramming languagemore detailed model, like theblock diagram viewcommitment to datapath FUs,registers, busses; register xferoperations are clock phase accuratemodel is in terms of logic gates;higher level MSI functionsdescribed in terms of theseelectrical behavior; accuratewaveformsSchematic capture + logic simulation package like PowerviewSpecial languages + simulation systems for describing the inherent parallel activity in hardwareLess AbstractMore AccurateSlower Simulation2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.10VHDL (VHSIC Hardware Description Language)° Goals:• Support design, documentation, and simulation of hardware• Digital system level to gate level• “Technology Insertion”° Concepts:• Design entity• Time-based execution model.Design Entity == Hardware ComponentInterface == External CharacteristicsArchitecture (Body ) == Internal Behavior or Structure2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.11Interface° Externally Visible Characterisitcs• Ports: channels of communication- (inputs, outputs, clocks, control)• Generic Parameters: define class of components- (timing characterisitcs, size, fan-out)--- determined where instantiated or by default° Internally Visible Characteristics• Declarations:• Assertions: constraints on all alternative bodies• (i.e., implmentations)InterfaceArchitectureview to other modulesdetails of implementation2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.12VHDL Example: nand gate ° Entity describes interface° Architecture give behavior, i.e., function° y is a signal, not a variable• it changes when ever the inputs change• drive a signal• NAND process is in an infinite loop° VLBit is 0, 1, X or ZENTITY nand is PORT (a,b: IN VLBIT; y: OUT VLBIT)END nandARCHITECTURE behavioral OF nand isBEGIN y <= a NAND b;END behavioral;2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.13Modeling Delays° Model temporal, as well as functional behavior, with delays in signalstatements; Time is one difference from programming languages° y changes 1 ns after a or b changes° This fixed delay is inflexible• hard to reflect changes in technologyENTITY nand is PORT (a,b: IN VLBIT; y: OUT VLBIT)END nandARCHITECTURE behavioral OF nand isBEGIN y <= a NAND b after 1 ns;END behavioral;2/8/99 ©UCB Spring 1999CS152 / KubiatowiczLec5.14Generic Parameters° Generic parameters provide default values• may be overidden on each instance• attach value to symbol as
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