CS 152 Computer Architecture and Engineering Lecture 26 Mid Term II Review 2006 11 30 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L26 Mid Term II Review UC Regents Fall 2006 UCB CS 152 What s left Today HKN Mid term II Review Homework II due in class Tuesday 12 5 Mid term II 6 00 9 00 PM 306 Soda No class 11 12 30 that day No electronic devices no notes leave backpacks in front of class 12 7 Final presentations Thursday Email slides to cs152 staff cory by 11 50 PM CS 152 L26 Mid Term II Review UC Regents Fall 2006 UCB Mid Term Review Session Homework II solutions Solution PDF will be on website soon after class Study guide for Mid Term II CS 152 L26 Mid Term II Review UC Regents Fall 2006 UCB Q1 Multithreading and Forwarding CS 152 L26 Mid Term II Review UC Regents Fall 2006 UCB Draw only NECESSARY inputs to Fwd muxes IF ID Decode EX IR IR IR MEM WB IR T1 PC T1 PC T2 T h d T2 T h d F w d A Y T h d F w d M M B 1 bit Thread Select R Q2 Write back no write on allocate cache L LRU bit L 1 indicates left set as drawn on page has been read or written most recently L 0 indicates right set has been read or written most recently Index 00 Setting V 0 does notCache updateTag L 28 bits 2 bits Cache DataValidCache Tags decimal V hex Left most recent L 12 1 0x0000001 0 16 1 0x0000000 5 1 0x0000002 8 0 0x0000000 1 word Main Memory 28 bits Addr 0x00000000 0x00000004 0x00000008 0x0000000C Addr in hex values in decimal CS 152 L17 Advanced Processors I Hit Left 0 1 0 Ex 0x01 Cache Tags Valid Cache Data Hit Right hex V decimal 0x0000002 1 20 0x0000001 1 24 0x0000000 1 7 0x0000002 1 13 Writes that miss cache 28 bits DO NOT allocate cache lines Value Addr Value 0x00000010 12 12 0x00000014 24 16 0x00000018 5 3 0x0000001C 14 13 1 word Addr 0x00000020 0x00000024 0x00000028 0x0000002C Value 20 16 7 15 UC Regents Fall 2005 UCB Instr 1 SW R0 16 R0 L LRU bit L 1 indicates left set as drawn on page has been read or written most recently L 0 indicates right set has been read or written most recently Index 00 Setting V 0 does notCache updateTag L 28 bits 2 bits Cache DataValidCache Tags decimal V hex Left most recent L 12 1 0x0000001 0 16 1 0x0000000 5 1 0x0000002 8 0 0x0000000 1 word Main Memory 28 bits Addr 0x00000000 0x00000004 0x00000008 0x0000000C Addr in hex values in decimal CS 152 L17 Advanced Processors I Hit Left 0 1 0 Ex 0x01 Cache Tags Valid Cache Data Hit Right hex V decimal 0x0000002 1 20 0x0000001 1 24 0x0000000 1 7 0x0000002 1 13 Writes that miss cache 28 bits DO NOT allocate cache lines Value Addr Value 0x00000010 12 12 0x00000014 24 16 0x00000018 5 3 0x0000001C 14 13 1 word Addr 0x00000020 0x00000024 0x00000028 0x0000002C Value 20 16 7 15 UC Regents Fall 2005 UCB Instr 1 SW R0 16 R0 L LRU bit L 1 indicates left set as drawn on page has been read or written most recently L 0 indicates right set has been read or written most recently Index 00 Setting V 0 does notCache updateTag L 28 bits 2 bits Cache DataValidCache Tags decimal V hex Left most recent L 0 1 0x0000001 1 16 1 0x0000000 5 1 0x0000002 8 0 0x0000000 1 word Main Memory 28 bits Addr 0x00000000 0x00000004 0x00000008 0x0000000C Addr in hex values in decimal CS 152 L17 Advanced Processors I Hit Left 0 1 0 Ex 0x01 Cache Tags Valid Cache Data Hit Right hex V decimal 0x0000002 1 20 0x0000001 1 24 0x0000000 1 7 0x0000002 1 13 Writes that miss cache 28 bits DO NOT allocate cache lines Value Addr Value 0x00000010 12 12 0x00000014 24 16 0x00000018 5 3 0x0000001C 14 13 1 word Addr 0x00000020 0x00000024 0x00000028 0x0000002C Value 20 16 7 15 UC Regents Fall 2005 UCB Instr 2 LW R20 20 R0 L LRU bit L 1 indicates left set as drawn on page has been read or written most recently L 0 indicates right set has been read or written most recently Index 00 Setting V 0 does notCache updateTag L 28 bits 2 bits Cache DataValidCache Tags decimal V hex Left most recent L 0 1 0x0000001 1 16 1 0x0000000 5 1 0x0000002 8 0 0x0000000 1 word Main Memory 28 bits Addr 0x00000000 0x00000004 0x00000008 0x0000000C Addr in hex values in decimal CS 152 L17 Advanced Processors I Hit Left 0 1 0 Ex 0x01 Cache Tags Valid Cache Data Hit Right hex V decimal 0x0000002 1 20 0x0000001 1 24 0x0000000 1 7 0x0000002 1 13 Writes that miss cache 28 bits DO NOT allocate cache lines Value Addr Value 0x00000010 12 12 0x00000014 24 16 0x00000018 5 3 0x0000001C 14 13 1 word Addr 0x00000020 0x00000024 0x00000028 0x0000002C Value 20 16 7 15 UC Regents Fall 2005 UCB Instr 2 LW R20 20 R0 no state change L LRU bit L 1 indicates left set as drawn on page has been read or written most recently L 0 indicates right set has been read or written most recently Index 00 Setting V 0 does notCache updateTag L 28 bits 2 bits Cache DataValidCache Tags decimal V hex Left most recent L 0 1 0x0000001 1 16 1 0x0000000 5 1 0x0000002 8 0 0x0000000 1 word Main Memory 28 bits Addr 0x00000000 0x00000004 0x00000008 0x0000000C Addr in hex values in decimal CS 152 L17 Advanced Processors I Hit Left 0 1 0 Ex 0x01 Cache Tags Valid Cache Data Hit Right hex V decimal 0x0000002 1 20 0x0000001 1 24 0x0000000 1 7 0x0000002 1 13 Writes that miss cache 28 bits DO NOT allocate cache lines Value Addr Value 0x00000010 12 12 0x00000014 24 16 0x00000018 5 3 0x0000001C 14 13 1 word Addr 0x00000020 0x00000024 0x00000028 0x0000002C Value 20 16 7 15 UC Regents Fall 2005 UCB Instr 3 LW R21 24 R0 L LRU bit L 1 indicates left set as drawn on page has been read or written most recently L 0 indicates right set has been read or written most recently Index 00 Setting V 0 does notCache updateTag L 28 bits 2 bits Cache DataValidCache Tags decimal V hex Left most recent L 0 1 0x0000001 1 16 1 0x0000000 5 1 0x0000002 8 0 0x0000000 1 word Main Memory 28 bits Addr 0x00000000 0x00000004 0x00000008 0x0000000C Addr in hex values in decimal CS 152 L17 Advanced Processors I Hit Left 0 1 0 Ex 0x01 Cache Tags Valid Cache Data Hit Right hex V decimal 0x0000002 1 20 0x0000001 1 24 0x0000000 1 7 0x0000002 1 13 Writes that miss cache 28 bits DO NOT allocate cache lines Value …
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