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Berkeley COMPSCI 152 - Lecture 26 – Mid­Term II Review

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Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47CS 152 L26: Mid-Term II Review UC Regents Fall 2006 © UCB2006-11-30John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 26 – Mid-Term II Reviewwww-inst.eecs.berkeley.edu/~cs152/TAs: Udam Saini and Jue SunCS 152 L26: Mid-Term II Review UC Regents Fall 2006 © UCBCS 152: What’s left ...Tuesday 12/5: Mid-term II, 6:00-9:00 PM, 306 Soda. No class 11-12:30 that day.No electronic devices, no notes,leave backpacks in front of class ...Today: HKN, Mid-term II Review.Homework II due in class.Thursday 12/7: Final presentations.Email slides to cs152-staff@cory by 11:50 PM.CS 152 L26: Mid-Term II Review UC Regents Fall 2006 © UCBMid-Term Review SessionHomework II solutionsSolution PDF will be on website soon after class.Study guide for Mid-Term IIUC Regents Fall 2006 © UCBCS 152 L26: Mid-Term II ReviewQ1: Multithreading and ForwardingIRIRBAMIRYMIRRID (Decode) EXMEMWB1 bitT1T2ThdFwdFwdIFPCT1PCT2ThdThdThread SelectDraw only NECESSARY inputs to Fwd muxesUC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors IQ2. Write-back, no write on allocate cacheCache Tag (28 bits)Index(2 bits)001110Cache Data(decimal)1216580x00000010x00000000x00000020x0000000Cache Tags(hex)Valid(V)Ex: 0x01=HitRight=HitLeft1 word0010Left most recent(L)1 word 28 bits28 bitsL: LRU bit. L = 1 indicates left set (as drawn on page) has been read or written most recently. L = 0 indicates right set has been read or written most recently. Setting V=0 does not update L.0x00000020x00000010x00000000x0000002111120247130x00000000120x00000004240x0000000850x0000000C14Addr Value Addr Value Addr ValueMain MemoryAddr in hex, values in decimalWrites that miss cache DO NOT allocate cache lines0x00000010120x00000014160x0000001830x0000001C130x00000020200x00000024160x0000002870x0000002C15Cache Data(decimal)Cache Tags(hex)Valid(V)UC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors ICache Tag (28 bits)Index(2 bits)001110Cache Data(decimal)1216580x00000010x00000000x00000020x0000000Cache Tags(hex)Valid(V)Ex: 0x01=HitRight=HitLeft1 word0010Left most recent(L)1 word 28 bits28 bitsL: LRU bit. L = 1 indicates left set (as drawn on page) has been read or written most recently. L = 0 indicates right set has been read or written most recently. Setting V=0 does not update L.0x00000020x00000010x00000000x0000002111120247130x00000000120x00000004240x0000000850x0000000C14Addr Value Addr Value Addr ValueMain MemoryAddr in hex, values in decimalWrites that miss cache DO NOT allocate cache lines0x00000010120x00000014160x0000001830x0000001C130x00000020200x00000024160x0000002870x0000002C15Cache Data(decimal)Cache Tags(hex)Valid(V)Instr 1: SW R0 16(R0)UC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors IInstr 1: SW R0 16(R0)Cache Tag (28 bits)Index(2 bits)001110Cache Data(decimal)016580x00000010x00000000x00000020x0000000Cache Tags(hex)Valid(V)Ex: 0x01=HitRight=HitLeft1 word1010Left most recent(L)1 word 28 bits28 bitsL: LRU bit. L = 1 indicates left set (as drawn on page) has been read or written most recently. L = 0 indicates right set has been read or written most recently. Setting V=0 does not update L.0x00000020x00000010x00000000x0000002111120247130x00000000120x00000004240x0000000850x0000000C14Addr Value Addr Value Addr ValueMain MemoryAddr in hex, values in decimalWrites that miss cache DO NOT allocate cache lines0x00000010120x00000014160x0000001830x0000001C130x00000020200x00000024160x0000002870x0000002C15Cache Data(decimal)Cache Tags(hex)Valid(V)UC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors ICache Tag (28 bits)Index(2 bits)001110Cache Data(decimal)016580x00000010x00000000x00000020x0000000Cache Tags(hex)Valid(V)Ex: 0x01=HitRight=HitLeft1 word1010Left most recent(L)1 word 28 bits28 bitsL: LRU bit. L = 1 indicates left set (as drawn on page) has been read or written most recently. L = 0 indicates right set has been read or written most recently. Setting V=0 does not update L.0x00000020x00000010x00000000x0000002111120247130x00000000120x00000004240x0000000850x0000000C14Addr Value Addr Value Addr ValueMain MemoryAddr in hex, values in decimalWrites that miss cache DO NOT allocate cache lines0x00000010120x00000014160x0000001830x0000001C130x00000020200x00000024160x0000002870x0000002C15Cache Data(decimal)Cache Tags(hex)Valid(V)Instr 2: LW R20 20(R0)UC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors IInstr 2: LW R20 20(R0) [no state change] Cache Tag (28 bits)Index(2 bits)001110Cache Data(decimal)016580x00000010x00000000x00000020x0000000Cache Tags(hex)Valid(V)Ex: 0x01=HitRight=HitLeft1 word1010Left most recent(L)1 word 28 bits28 bitsL: LRU bit. L = 1 indicates left set (as drawn on page) has been read or written most recently. L = 0 indicates right set has been read or written most recently. Setting V=0 does not update L.0x00000020x00000010x00000000x0000002111120247130x00000000120x00000004240x0000000850x0000000C14Addr Value Addr Value Addr ValueMain MemoryAddr in hex, values in decimalWrites that miss cache DO NOT allocate cache lines0x00000010120x00000014160x0000001830x0000001C130x00000020200x00000024160x0000002870x0000002C15Cache Data(decimal)Cache Tags(hex)Valid(V)UC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors ICache Tag (28 bits)Index(2 bits)001110Cache Data(decimal)016580x00000010x00000000x00000020x0000000Cache Tags(hex)Valid(V)Ex: 0x01=HitRight=HitLeft1 word1010Left most recent(L)1 word 28 bits28 bitsL: LRU bit. L = 1 indicates left set (as drawn on page) has been read or written most recently. L = 0 indicates right set has been read or written most recently. Setting V=0 does not update L.0x00000020x00000010x00000000x0000002111120247130x00000000120x00000004240x0000000850x0000000C14Addr Value Addr Value Addr ValueMain MemoryAddr in hex, values in decimalWrites that miss cache DO NOT allocate cache lines0x00000010120x00000014160x0000001830x0000001C130x00000020200x00000024160x0000002870x0000002C15Cache Data(decimal)Cache Tags(hex)Valid(V)Instr 3: LW R21 24(R0)UC Regents Fall 2005 © UCBCS 152 L17: Advanced Processors IInstr 3: LW R21 24(R0) Cache Tag


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Berkeley COMPSCI 152 - Lecture 26 – Mid­Term II Review

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