C152 Laboratory Exercise 3Professor: Krste AsanovicTA: Scott BeamerDepartment of Electrical Engineering & Computer ScienceUniversity of California, BerkeleyMarch 3, 20091 Introduction and goalsThe goal of this laboratory assignment is to allow you to conduct some simple virtual experimentsin the Simics simulation environment. Using the x86-tlb module, you will collect virtual statisticsand make some architectural recommendations based on the results.The lab has two sections, a directed portion and an open–ended portion. Everyone will do thedirected portion the same way, and grades will be assigned based on correctness. The open–endedportion will allow you to pursue more creative investigations, and your grade will be based on theeffort made to complete the task or the arguments you provide in support of your ideas.Students are encouraged to discuss solutions to the lab assignments with other students, butmust run through the directed portion of the lab by themselves and turn in their own lab report.For the open-ended portion of each lab, students can work individually or in groups of two orthree. Any open-ended lab assignment completed as a group should be written up and handed inseparately. Students are free to take part in different groups for different lab assignments.You are only required to do one of the open ended assignments. These assignments are ingeneral starting points or suggestions. Alternatively, you can propose and complete your own openended project as long as it is sufficiently rigorous. If you feel uncertain about the rigor of a proposal,feel free to consult the TA or professor.This lab assumes you have completed the earlier laboratory assignments. However, we willre-include all the relevant files from past labs in this lab’s distribution bundle for your convenience.Furthermore, we will assume that you remember all the commands used in earlier labs for controllingSimics simulation. If you feel any confusion about these points, feel free to consult the first labguide or the Simics User Guide.It is also important to stress that how concise the report is and how the data is presented willbe taken into account when grading. Problems usually are specific about what statistic they want,so there is no need to give all. Tables and especially graphs are much more efficient and effectiveways to communicate data.1.1 Simics TLB OverviewFor this lab we will be using the x86-tlb module, as it is the most customizable and accessible ofthe processor TLBs available in Simics. In order to use this module, we must simulate an x861processor. Simics can actually simulate many x86 processors (Intel Pentium II, III, IV and AMDHammer64) using a single target module (x86–440bx). We will use the Tango machine providedwith Simics, which is a Pentium IV running Fedora Linux.The x86-tlb module is not especially well documented in the materials available from Virtutech,so we will provide you with a summary of the relevant information here. We will also provideadditional details about specific commands as they are needed throughout the lab.1.1.1 Background on x86 Page TablesThe x86 architecture uses a three level page table hierarchy, similar to the one discussed in class.A first level page is referred to as a page directory, and a second level page is referred to as a pagetable. A page directory contains 1024 page directory entries (PDEs), each of which can point toa page table. A page table contains 1024 page table entries (PTEs), each of which can point to apage frame. Therefore, a virtual address is divided into three components, each of which indexesone of these structures: a 10-bit directory index, a 10-bit page index and a 12-bit offset.Actually, the system is slightly more complicated, as large pages are also allowed. These pagescan be either 2 or 4 megabytes depending on operating system settings. The version of FedoraLinux running on our target machine requires that these large pages be 4MB (it also calls themhuge pages).On a TLB miss this page table is walked by the hardware.1.1.2 Simics x86–tlb TLBsOur simulator actually has four TLBs. Each TLB caches a different sort of address translation(4KB data, 4KB instruction, 4MB data, 4MB instruction). The size and associativity of the 4KBTLBs can be configured separately from the size and associativity of the 4MB TLBs, but theinstruction and data versions of each must be the same size. The default values are 64 entries,4–way set associative for the 4KB TLBs and 8 entries, 4–way set associative for the 4MB TLBs.The values can be changed by recompiling the module.1.1.3 TLB statistics and loggingUnfortunately, the TLBs do not come with statistics gathering commands like those we used tomeasure cache performance. However, they do generate certain types of simulation events (whichSimics calls haps). You will be provided with scripts which monitor these events and then use themto provide you with a summary of TLB statistics. You can also change the log–level attribute of theTLB module to see notifications of certain types of events (e.g. flushes). The following statisticswill be tracked for you:TLB Fills. Triggered when a TLB entry is filled after a tablewalk.TLB Invalidates. Triggered when a TLB entry is invalidated. TLB flushes generate multipleinvalidate haps.TLB Replaces. Triggered when one TLB entry is replaced by another.TLB Misses. Triggered when a TLB miss occurs. Not tracked separately for 4KB and 4MBTLBs.2These statistics record only the total number of these events, so it is up to you to keep track ofthe number of instructions executed during which these events were recorded. If you do not, anycomparative analysis you undertake will have no meaning.1.2 Graded ItemsYou will turn a hard copy of your results to the professor or TA. Please label each section of theresults clearly. The following items need to be turned in for evaluation:1. Problem 2.3: TLB statistics for each configuration and answers2. Problem 2.4: TLB statistics for both sizes and answers3. Problem 2.5: TLB statistics during boot and answers4. Problem 2.6: TLB statistics for both programs and answers5. Problem 3.1/3.2/3.3/3.4 modifications and evaluations (include source code if required)2 Directed Portion2.1 General methodologyUnlike g–caches, TLBs are a core part of the x86 target’s functionality, and operate constantly. It istherefore unnecessary to ‘warm’ them the way we had to with the caches. While you must insure youare capturing a
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