CS 152 Computer Architecture and Engineering Lecture 7 Memory Hierarchy II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 Last time in Lecture 6 Dynamic RAM DRAM is main form of main memory storage in use today Holds values on small capacitors need refreshing hence dynamic Slow multi step access precharge read row read column Static RAM SRAM is faster but more expensive Used to build on chip memory for caches Caches exploit two forms of predictability in memory reference streams Temporal locality same location likely to be accessed again soon Spatial locality neighboring location likely to be accessed soon Cache holds small set of values in fast memory SRAM close to processor Need to develop search scheme to find values in cache and replacement policy to make space for newly accessed locations 2 14 2008 CS152 Spring 08 2 Relative Memory Cell Sizes On Chip SRAM in logic chip DRAM on memory chip QuickTime and a TIFF Uncompressed decompressor are needed to see this picture Foss Implementing Application Specific Memory ISSCC 1996 QuickTime and a TIFF Uncompressed decompressor are needed to see this picture 2 14 2008 CS152 Spring 08 3 Placement Policy Block Number 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 1 1 0 1 2 3 4 5 6 7 8 9 8 9 2 2 2 2 2 2 2 2 3 3 2 2 0 1 2 3 4 5 0 1 6 7 8 9 Memory Set Number 0 2 1 3 0 1 2 3 4 5 6 7 Cache Fully 2 way Set Associative Associative anywhere anywhere in block 12 set 0 can be placed 12 mod 4 2 14 2008 CS152 Spring 08 Direct Mapped only into block 4 12 mod 8 4 Direct Mapped Cache Tag Index t V Tag k Block Offset Data Block b 2k lines t HIT 2 14 2008 Data Word or Byte CS152 Spring 08 2 Way Set Associative Cache Tag t Block Offset Index k V Tag Data Block b V Tag Data Block t Data Word or Byte HIT 2 14 2008 CS152 Spring 08 Fully Associative Cache V Tag Data Block t Tag t Block Offset HIT b 2 14 2008 Data Word or Byte CS152 Spring 08 Replacement Policy In an associative cache which block from a set should be evicted when the set becomes full Random Least Recently Used LRU LRU cache state must be updated on every access true implementation only feasible for small sets 2way pseudo LRU binary tree often used for 4 8 way First In First Out FIFO a k a Round Robin used in highly associative caches Not Least Recently Used NLRU FIFO with exception for most recently used block or blocks Replacement only happens on misses 2 14 2008 CS152 Spring 08 8 Block Size and Spatial Locality Block is unit of transfer between the cache and memory Tag Word0 Split CPU block address Word1 Word2 Word3 address 4 word block b 2 offsetb b bits 32 b bits 2b block size a k a line size in bytes Larger block size has distinct hardware advantages less tag overhead exploit fast burst transfers from DRAM exploit fast burst transfers over wide busses What are the disadvantages of increasing block size 2 14 2008 CS152 Spring 08 9 CPU Cache Interaction 5 stage pipeline 0x4 E Add M A nop PC addr inst IR D Decode Register Fetch ALU Y Primary Data rdata Cache hit wdata wdata B hit PCen Primary Instruction Cache MD1 we addr R MD2 Stall entire CPU on data cache miss To Memory Control Cache Refill Data from Lower Levels of Memory Hierarchy What about Instruction miss or writes to istream 2 14 2008 CS152 Spring 08 10 Improving Cache Performance Average memory access time Hit time Miss rate x Miss penalty To improve performance reduce the hit time reduce the miss rate reduce the miss penalty What is the simplest design strategy 2 14 2008 CS152 Spring 08 11 Causes for Cache Misses Compulsory first reference to a block a k a cold start misses misses that would occur even with infinite cache Capacity needed cache is too small to hold all data by the program misses that would occur even under perfect replacement policy Conflict misses that occur because of collisions due to block placement strategy misses that would not occur with full associativity 2 14 2008 CS152 Spring 08 12 Effect of Cache Parameters on Performance Larger cache size Higher associativity Larger block size 2 14 2008 CS152 Spring 08 13 Write Policy Choices Cache hit write through write both cache memory generally higher traffic but simplifies cache coherence write back write cache only memory is written only when the entry is evicted a dirty bit per block can further reduce the traffic Cache miss no write allocate only write to main memory write allocate aka fetch on write fetch into cache Common combinations 2 14 2008 write through and no write allocate write back with write allocate CS152 Spring 08 14 Write Performance Tag Block Offset Index b t V Tag k Data 2k lines t HIT 2 14 2008 WE Data Word or Byte CS152 Spring 08 15 Reducing Write Hit Time Problem Writes take two cycles in memory stage one cycle for tag check plus one cycle for data write if hit Solutions Design data RAM that can perform read and write in one cycle restore old value after tag miss Fully associative CAM Tag caches Word line only enabled if hit Pipelined writes Hold write data for store in single buffer ahead of cache write cache data during next store s tag check 2 14 2008 CS152 Spring 08 16 Pipelining Cache Writes Address and Store Data From CPU Tag Index Store Data Delayed Write Addr Delayed Write Data Load Store S L Tags Data 1 Hit 0 Load Data to CPU Data from a store hit written into data portion of cache during tag access of 2 14 2008 CS152 Spring 08 17 CS152 Administrivia Krste no office hours Monday 2 18 President s Day Holiday email for alternate time Henry office hours 511 Soda None on Monday due to holiday 2 00 3 00PM Fridays In class quiz dates Q1 Tuesday February 19 ISAs microcode simple pipelining Material covered Lectures 1 5 PS1 Lab 1 We re stuck in this room for semester nothing else open 2 14 2008 CS152 Spring 08 18 Write Buffer to Reduce Read Miss Penalty CPU Data Cache Write buffe r RF Unified L2 Cache Evicted dirty lines for writeback cache OR All writes in writethru cache Processor is not stalled on writes and read misses can go ahead of write to main memory Problem Write buffer may hold updated value of location needed by a read miss Simple scheme on a read miss wait for the write buffer to go empty Faster scheme Check write buffer addresses against read miss addresses if no match allow read miss to go ahead of …
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