CS152 Computer Architecture and Engineering Lecture 13 Introduction to Pipelining II Control March 15 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Recap Sequential Laundry 6 PM T a s k O r d e r A 7 8 9 10 11 12 1 2 AM 3030 30 30 3030 30 30 3030 30 30 3030 30 30 Time B C D Sequential laundry takes 8 hours for 4 loads If they learned pipelining how long would laundry take CS152 Kubiatowicz 3 15 99 UCB Spring 1999 Recap Pipelining Lessons its intuitive 6 PM T a s k O r d e r 3 15 99 7 8 9 Time 3030 30 30 30 3030 A Pipelining doesn t help latency of single task it helps throughput of entire workload Multiple tasks operating simultaneously using different resources B Potential speedup Number pipe stages C Pipeline rate limited by slowest pipeline stage D Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup Stall for Dependences CS152 Kubiatowicz UCB Spring 1999 Recap Ideal Pipelining IF DCD IF Assume instructions are completely independent EX DCD IF MEM WB EX MEM WB EX MEM WB EX MEM WB EX MEM DCD IF DCD IF DCD WB Maximum Speedup Number of stages Speedup Time for unpipelined operation Time for longest stage Example 40ns data path 5 stages Longest stage is 10 ns Speedup 4 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Recap Can pipelining get us into trouble Yes Pipeline Hazards structural hazards attempt to use the same resource two different ways at the same time e g multiple memory accesses multiple register writes solutions multiple memories stretch pipeline control hazards attempt to make a decision before condition is evaulated e g any conditional branch solutions prediction delayed branch data hazards attempt to use item before it is ready e g add r1 r2 r3 sub r4 r1 r5 lw r6 0 r7 or r8 r6 r9 3 15 99 solutions forwarding bypassing stall bubble UCB Spring 1999 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topics Recap last lecture Pipelined Control Do it yourself Pipelined Control Administrivia Hazards Forwarding Exceptions Review MIPS R3000 pipeline Advanced Pipelining 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Control and Datapath Split state diag into 5 pieces IR Mem PC PC PC 4 A R rs B R rt S A SX M Mem S Mem S B M Data Mem B UCB Spring 1999 Reg File S D 3 15 99 If Cond PC PC SX Mem Access A Exec R rd M IR Inst Mem R rt S PC Next PC R rd S S A SX Equal S A or ZX Reg File S A B CS152 Kubiatowicz Pipelined Processor almost for slides D Reg File M Data Mem B Mem Access PC Next PC Equal IRmem WB Ctrl Ex Ctrl Exec S IRwb IRex A Mem Ctrl Dcd Ctrl Reg File IR Inst Mem Valid What happens if we start a new instruction every cycle 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Pipelining the Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Clock 1st lw Ifetch Reg Dec 2nd lw Ifetch 3rd lw Exec Mem Wr Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr The five independent functional units in the pipeline datapath are Instruction Memory for the Ifetch stage Register File s Read ports bus A and busB for the Reg Dec stage ALU for the Exec stage Data Memory for the Mem stage Register File s Write port bus W for the Wr stage 3 15 99 UCB Spring 1999 CS152 Kubiatowicz The Four Stages of Rtype Cycle 1 Cycle 2 Cycle 3 R type Ifetch Reg Dec Exec Cycle 4 Wr Ifetch Instruction Fetch Fetch the instruction from the Instruction Memory Reg Dec Registers Fetch and Instruction Decode Exec ALU operates on the two register operands Update PC Wr Write the ALU output back to the register file 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Pipelining the R type and Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R type Ifetch R type Reg Dec Exec Ifetch Reg Dec Exec Ifetch Reg Dec Load Ops We have a problem Wr R type Ifetch Wr Exec Mem Wr Reg Dec Exec Wr R type Ifetch Reg Dec Exec Wr We have pipeline conflict or structural hazard Two instructions try to write to the register file at the same time Only one write port 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Important Observation Each functional unit can only be used once per instruction Each functional unit must be used at the same stage for all instructions Load uses Register File s Write Port during its 5th stage Load 1 2 Ifetch Reg Dec 3 Exec 4 5 Mem Wr R type uses Register File s Write Port during its 4th stage 1 R type Ifetch 2 Reg Dec 3 Exec 4 Wr 2 ways to solve this pipeline hazard 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Solution 1 Insert Bubble into the Pipeline Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock Ifetch Load Reg Dec Exec Ifetch Reg Dec R type Ifetch Wr Exec Mem Reg Dec Exec Wr Wr R type Ifetch Reg Dec Pipeline Exec R type Ifetch Bubble Reg Dec Ifetch Wr Exec Reg Dec Wr Exec Insert a bubble into the pipeline to prevent 2 writes at the same cycle The control logic can be complex Lose instruction fetch and issue opportunity No instruction is started in Cycle 6 3 15 99 UCB Spring 1999 CS152 Kubiatowicz Solution 2 Delay R type s Write by One Cycle Delay R type s register write by one cycle Now R type instructions also use Reg File s write port at Stage 5 Mem stage is a NOOP stage nothing is being done 1 2 R type Ifetch Cycle 1 Cycle 2 Reg Dec 3 Exec 4 Mem 5 Wr Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R type Ifetch R type Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr Reg Dec Exec Mem Wr Reg Dec Exec Mem Load R type Ifetch R type Ifetch 3 15 99 UCB Spring 1999 Wr CS152 Kubiatowicz Modified Control Datapath IR Mem PC PC PC 4 A R rs B R rt S A SX M S M Mem S Mem S B Data Mem B UCB Spring 1999 Reg File M S D 3 15 99 if Cond PC PC SX Mem Access A Exec R rd M IR Inst Mem R rt M PC Next PC R rd M S A SX Equal …
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