CS152 Computer Architecture and Engineering Lecture 13 Introduction to Pipelining II: ControlRecap: Sequential LaundryRecap: Pipelining Lessons (its intuitive!)Recap: Ideal PipeliningRecap: Can pipelining get us into trouble?The Big Picture: Where are We Now?Control and Datapath: Split state diag into 5 piecesPipelined Processor (almost) for slidesPipelining the Load InstructionThe Four Stages of R-typePipelining the R-type and Load InstructionImportant ObservationSolution 1: Insert “Bubble” into the PipelineSolution 2: Delay R-type’s Write by One CycleModified Control & DatapathThe Four Stages of StoreThe Three Stages of BeqControl DiagramData Stationary ControlDatapath + Data Stationary ControlAdministriviaLet’s Try it OutStart: Fetch 10Fetch 14, Decode 10Fetch 20, Decode 14, Exec 10Fetch 24, Decode 20, Exec 14, Mem 10Fetch 30, Dcd 24, Ex 20, Mem 14, WB 10Fetch 100, Dcd 30, Ex 24, Mem 20, WB 14Fetch 104, Dcd 100, Ex 30, Mem 24, WB 20Fetch 110, Dcd 104, Ex 100, Mem 30, WB 24Fetch 114, Dcd 110, Ex 104, Mem 100, WB 30Pipeline Hazards AgainData HazardsHazard DetectionRecord of Pending WritesResolve RAW by forwardingWhat about memory operations?Compiler Avoiding Load Stalls:What about Interrupts, Traps, Faults?Exception HandlingException ProblemResolution: Freeze above & Bubble BelowFYI: MIPS R3000 clocking disciplineMIPS R3000 Instruction PipelineRecall: Data Hazard on r1MIPS R3000 Multicycle OperationsIssues in Pipelined designHistorical PerspectiveTechnology PerspectivePartitioned Instruction Issue (simple Superscalar)Example: DAXPYUnrollingSoftware PipeliningMultiple Pipes/ Harder SuperscalarBranch penalties in superscalarSummary: PipeliningSummary3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.1CS152Computer Architecture and EngineeringLecture 13Introduction to Pipelining II:ControlMarch 15, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.2Recap: Sequential Laundry°Sequential laundry takes 8 hours for 4 loads°If they learned pipelining, how long would laundry take? 30TaskOrderBCDATime3030 3030 30 3030 3030 3030 3030 30306 PM78910111212 AM3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.3Recap: Pipelining Lessons (its intuitive!)°Pipelining doesn’t help latency of single task, it helps throughput of entire workload°Multiple tasks operating simultaneously using different resources°Potential speedup = Number pipe stages°Pipeline rate limited by slowest pipeline stage°Unbalanced lengths of pipe stages reduces speedup°Time to “fill” pipeline and time to “drain” it reduces speedup°Stall for Dependences6 PM7 8 9TimeBCDA303030 30303030TaskOrder3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.4Recap: Ideal PipeliningIF DCD EX MEM WBIF DCD EX MEM WBIF DCD EX MEM WBIF DCD EX MEM WBIF DCD EX MEM WBMaximum Speedup Number of stagesSpeedup Time for unpipelined operation Time for longest stageExample: 40ns data path, 5 stages, Longest stage is 10 ns, Speedup 4Assume instructionsare completely independent!3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.5Recap: Can pipelining get us into trouble?Yes: Pipeline Hazards•structural hazards: attempt to use the same resource two different ways at the same time-e.g., multiple memory accesses, multiple register writes-solutions: multiple memories, stretch pipeline•control hazards: attempt to make a decision before condition is evaulated-e.g., any conditional branch-solutions: prediction, delayed branch•data hazards: attempt to use item before it is ready-e.g., add r1,r2,r3; sub r4, r1 ,r5; lw r6, 0(r7); or r8, r6 ,r9-solutions: forwarding/bypassing, stall/bubble3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.6°The Five Classic Components of a Computer°Today’s Topics: •Recap last lecture•Pipelined Control/ Do it yourself Pipelined Control•Administrivia•Hazards/Forwarding•Exceptions•Review MIPS R3000 pipeline•Advanced Pipelining?The Big Picture: Where are We Now? ControlDatapathMemoryProcessorInputOutput3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.7Control and Datapath: Split state diag into 5 piecesIR <- Mem[PC]; PC <– PC+4;A <- R[rs]; B<– R[rt]S <– A + B;R[rd] <– S;S <– A + SX;M <– Mem[S]R[rd] <– M;S <– A or ZX;R[rt] <– S;S <– A + SX;Mem[S] <- BIf CondPC < PC+SX;ExecReg. FileMemAccessDataMemABSRegFileEqualPCNext PCIRInst. MemDM3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.8Pipelined Processor (almost) for slides°What happens if we start a new instruction every cycle?ExecReg. FileMemAccessDataMemABSMRegFileEqualPCNext PCIRInst. MemValidIRexDcd CtrlIRmemEx CtrlIRwbMem CtrlWB CtrlD3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.9Pipelining the Load Instruction°The five independent functional units in the pipeline datapath are:•Instruction Memory for the Ifetch stage•Register File’s Read ports (bus A and busB) for the Reg/Dec stage•ALU for the Exec stage•Data Memory for the Mem stage•Register File’s Write port (bus W) for the Wr stageClockCycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7Ifetch Reg/Dec Exec Mem Wr1st lwIfetch Reg/Dec Exec Mem Wr2nd lwIfetch Reg/Dec Exec Mem Wr3rd lw3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.10The Four Stages of R-type°Ifetch: Instruction Fetch•Fetch the instruction from the Instruction Memory°Reg/Dec: Registers Fetch and Instruction Decode°Exec: •ALU operates on the two register operands•Update PC°Wr: Write the ALU output back to the register fileCycle 1 Cycle 2 Cycle 3 Cycle 4Ifetch Reg/Dec Exec WrR-type3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.11Pipelining the R-type and Load Instruction°We have pipeline conflict or structural hazard:•Two instructions try to write to the register file at the same time!•Only one write portClockCycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Ifetch Reg/Dec Exec WrR-typeIfetch Reg/Dec Exec WrR-typeIfetch Reg/Dec Exec Mem WrLoadIfetch Reg/Dec Exec WrR-typeIfetch Reg/Dec Exec WrR-typeOps! We have a problem!3/15/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec13.12Important Observation°Each functional unit can only be used once per instruction°Each functional unit must be used at the same stage for all instructions:•Load uses Register File’s Write Port during its 5th stage•R-type uses Register File’s Write Port during its 4th stageIfetch
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