Recap Summary from last time 5 steps to design a processor CS152 Computer Architecture and Engineering Lecture 8 1 Analyze instruction set datapath requirements 2 Select set of datapath components establish clock methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer Designing Single Cycle Control 5 Assemble the control logic MIPS makes it easier Instructions same size Feb 22 1999 Source registers always in same place John Kubiatowicz http cs berkeley edu kubitron Immediates same size location Operations always on registers immediates lecture slides http www inst eecs berkeley edu cs152 2 22 99 CS152 Kubiatowicz Lec8 1 UCB Spring 1999 Recap The MIPS Instruction Formats Single cycle datapath CPI 1 CCT long 2 22 99 Recap The MIPS Subset All MIPS instructions are 32 bits long The three instruction formats 31 26 op R type rs 6 bits 31 I type 26 op 31 16 rt 5 bits 5 bits 21 rs 6 bits J type 21 5 bits 11 6 0 rd shamt funct 5 bits 5 bits 6 bits 16 5 bits 0 0 OR Imm ori rt rs imm16 16 bits 26 target address 6 bits 31 ADD and subtract add rd rs rt sub rd rs rt immediate rt op CS152 Kubiatowicz Lec8 2 UCB Spring 1999 26 op 6 bits 31 21 rs 5 bits 26 op 5 bits 21 rs 6 bits 16 rt 5 bits 11 6 shamt funct 5 bits 5 bits 6 bits 16 rt 5 bits 0 rd 0 immediate 16 bits LOAD and STORE lw rt rs imm16 sw rt rs imm16 26 bits The different fields are op operation of the instruction rs rt rd the source and destination registers specifier shamt shift amount BRANCH beq rs rt imm16 funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of the jump instruction 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Lec8 3 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Lec8 4 Recap A Single Cycle Datapath The Big Picture Where are We Now We have everything except control signals underline Today s lecture will show you how to generate the control signals The Five Classic Components of a Computer Instruction 31 0 1 Mux 0 RegWr 5 Rt ALUctr Zero 16 Extender imm16 1 32 Rs Rd Input Control Memory Imm16 MemtoReg MemWr Datapath Output 0 32 32 WrEn Adr Data In 32 Clk Mux busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Mux 32 Clk Rt 5 ALU busW Rs 5 Processor 0 15 Clk 11 15 Rt 16 20 Rd RegDst Instruction Fetch Unit 21 25 nPC sel 1 Data Memory Today s Topic Designing the Control for the Single Cycle Datapath ALUSrc 2 22 99 ExtOp UCB Spring 1999 CS152 Kubiatowicz Lec8 5 2 22 99 CS152 Kubiatowicz Lec8 6 UCB Spring 1999 RTL The Add Instruction Outline of Today s Lecture 31 26 op Recap and Introduction 10 minutes 6 bits 21 rs 5 bits 16 rt 5 bits 11 6 0 rd shamt funct 5 bits 5 bits 6 bits Control for Register Register Or Immediate instructions 10 minutes add rd rs rt Questions and Administrative Matters 5 minutes Control signals for Load Store Branch Jump 15 minutes Building a local controller ALU Control 10 minutes mem PC Fetch the instruction from memory R rd R rs R rt The actual operation PC PC 4 Calculate the next instruction s address Break 5 minutes The main controller 20 minutes Summary 5 minutes 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Lec8 7 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Lec8 8 Instruction Fetch Unit at the Beginning of Add The Single Cycle Datapath during Add 31 Fetch the instruction from Instruction memory Instruction mem PC This is the same for all instructions 26 21 op 16 rs 11 rt 6 rd 0 shamt funct R rd R rs R rt Instruction 31 0 Rd RegDst 1 nPC sel RegWr 1 5 00 Rd Imm16 Zero 16 MemWr 0 0 32 Mux Extender PC Mux CS152 Kubiatowicz Lec8 9 32 1 WrEn Adr 1 Data In 32 32 Data Memory Clk ExtOp x 2 22 99 31 21 rs 16 0 rt immediate R rt R rs or ZeroExt Imm16 Instruction 31 0 RegWr 4 Rt ALUctr Zero Extender PC Mux Adder 16 1 32 Rs Rd Imm16 MemtoReg MemWr 0 32 32 WrEn Adr Data In 32 Clk Mux 00 Rt 5 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 imm16 1 5 Mux Adder 32 Clk Rs 5 ALU busW Clk 0 15 nPC sel Rt 1 Mux 0 11 15 Rd RegDst Instruction Fetch Unit 16 20 nPC sel Instruction 31 0 Adr 1 Data Memory ALUSrc Clk UCB Spring 1999 26 op 21 25 Inst Memory CS152 Kubiatowicz Lec8 10 UCB Spring 1999 The Single Cycle Datapath during Or Immediate PC PC 4 This is the same for all instructions except Branch and Jump imm16 Rs ALUSrc 0 UCB Spring 1999 0 Rt MemtoReg 0 Clk Instruction Fetch Unit at the End of Add 2 22 99 ALUctr Add Rt 5 ALU 32 Clk imm16 Adder imm16 Rs 5 Mux Adder PC Ext 2 22 99 Clk busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 busW 4 Rt 1 Mux 0 0 15 Adr Instruction Fetch Unit 11 15 nPC sel 4 16 20 Instruction 31 0 21 25 Inst Memory CS152 Kubiatowicz Lec8 11 2 22 99 ExtOp UCB Spring 1999 CS152 Kubiatowicz Lec8 12 The Single Cycle Datapath during Or Immediate 31 26 21 op 16 rs The Single Cycle Datapath during Load 0 rt 31 26 immediate 21 op R rt R rs or ZeroExt Imm16 16 rs 0 rt immediate R rt Data Memory R rs SignExt imm16 Instruction 31 0 imm16 16 2 22 99 ExtOp 0 UCB Spring 1999 CS152 Kubiatowicz Lec8 13 0 32 Data In 32 1 32 Data Memory Clk 32 ExtOp 1 2 22 99 CS152 Kubiatowicz Lec8 14 UCB Spring 1999 The Single Cycle Datapath during Store 31 26 0 rt immediate Instruction 31 0 Rt ALUctr Zero 32 Rd Imm16 MemtoReg MemWr 0 32 32 WrEn Adr Data In 32 Clk Mux ALU Extender 16 1 Rs 0 15 Rt 5 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 imm16 Meet at LaVal s pizza after the midterm Need a headcount How many are definitely coming 5 11 15 Rs 5 Mux 32 Clk Midterm reminders Pencil calculator two 8 5 x 11 pages of handwritten notes Sit in every other chair every other row odd row odd seat Clk 1 Mux 0 RegWr busW Rt Instruction Fetch Unit 16 20 nPC sel RegDst CS152 Kubiatowicz Lec8 15 16 rs Data Memory R rs SignExt imm16 R rt Rd Midterm next Wednesday 3 3 5 30pm to 8 30pm 277 Cory Hall Make up quiz on Tuesday No class on that …
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