Review from last time Design Process Design Entry Schematics HDL Compilers High Level Analysis Simulation Testing Assertions CS152 Computer Architecture and Engineering Lecture 6 Technology Mapping Turn design into physical implementation Low Level Analysis Check out Timing Setup Hold etc Verilog Three programming styles Structural Like a Netlist Instantiation of modules wires between them Verilog finish Multiply Divide Shift Dataflow Higher Level Expressions instead of gates February 11 2004 Behavioral Hardware programming Full flow control mechanisms Registers variables John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 File I O consol display etc 2 11 03 Verilog subtlety Blocking Assignments Verilog subtlety Non Blocking Assignments Blocking Assignments Assignments happen more like programming language sequential code Both Right and left sides evaluated completely Wait until assignment before going on Non blocking Assignments All right hand sides evaluated immediately Then assignments occur If no delays often want output ports to be assigned with non blocking assignments Example Can cause unexpected results when connecting output to logic in other always blocks Also a bit strange with delays on left hand side LHS Example reg E always begin E C end 2 11 03 C posedge clk A E E A C UCB Spring 2004 CS152 Kubiatowicz Lec6 2 UCB Spring 2004 CS152 Kubiatowicz Lec6 3 reg E C always posedge clk begin E A C E end E A 2 11 03 C UCB Spring 2004 CS152 Kubiatowicz Lec6 4 Sequential Logic Revisited better scheduling Must be careful mixing zero time blocking assignments and edge triggering Probably won t do what you expect when connecting it to other things module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q D endmodule FF Good Doesn t output until after edge Probably Not what you Expect Hold time of 5 units glitches 5 units ignored 2 11 03 A final word on Verilog Verilog does not turn hardware design into writing programs Since Verilog looks similar to programming languages some think that they can design hardware by writing programs NOT SO module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q 5 D endmodule FF Good Outputs 5 units after edge module FF CLK Q D input D CLK output Q reg Q always posedge CLK 5 Q D endmodule FF UCB Spring 2004 CS152 Kubiatowicz Lec6 5 How Program FPGA Generic Design Flow Verilog is a hardware description language The best way to use it is to first figure out the circuit you want then figure out how to describe it in Verilog The behavioral construct hides a lot of the circuit details but you as the designer must still manage the structure data communication Parallelism timing of your design Not doing so leads to very inefficient designs Read the document on non blocking assignment in Verilog that I put up on the handouts page Lots of very interesting things 2 11 03 CS152 Kubiatowicz Lec6 6 UCB Spring 2004 Idealized FPGA Logic Block Logic Block latch set by configuration bit stream 1 INPUTS Design Entry FF OUTPUT 0 Create your design files using 4 LUT schematic editor or hardware description language Verilog VHDL 4 input look up table Design implementation on FPGA Partition place and route PPR to create bit stream file Divide into CLB sized pieces place into blocks route to blocks 4 input Look Up Table 4 LUT implements combinational logic functions Register Design verification Use Simulator to check function Other software determines max clock frequency Load onto FPGA device cable connects PC to board optionally stores output of LUT Latch determines whether read reg or LUT check operation at full speed in real environment 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Lec6 7 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Lec6 8 4 LUT Implementation LUT as general logic gate INPUTS latch latch 16 latch 16 x 1 mux OUTPUT n bit LUT is actually implemented as a 2n x 1 memory inputs choose one of 2n memory locations memory locations latches are normally loaded with values from user s configuration bit stream Inputs to mux control are the CLB Configurable Logic Block inputs 2 11 03 Example 4 lut INPUTS Each latch location holds value of function corresponding to one input combination 0000 0001 0010 0011 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Example 2 lut INPUTS AND OR Result is a general purpose logic gate latch An n lut as a direct implementation of a function truth table 00 01 10 11 n LUT can implement any function of n inputs 0 0 0 1 0 1 1 1 Implements any function of 2 inputs Latches programmed as part of configuration bit stream How many functions of n inputs CS152 Kubiatowicz Lec6 9 UCB Spring 2004 2 11 03 F 0 0 0 0 F 0 0 0 1 F 0 0 1 0 F 0 0 1 1 UCB Spring 2004 store in 1st latch store in 2nd latch CS152 Kubiatowicz Lec6 10 Block RAM Extra RAM not using LUTs Additional application Distributed RAM RAM16X1S LUT Implements Single and Dual Ports Cascade LUTs to increase RAM size O Block RAM RAM32X1S D WE WCLK A0 A1 A2 A3 A4 Synchronous write Synchronous Asynchronous read or LUT Accompanying flip flops used for synchronous read LUT Spartan IIE True Dual Port Block RAM Port B D WE WCLK A0 A1 A2 A3 Port A CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Most efficient memory implementation O Dedicated blocks of memory Ideal for most memory requirements RAM16X2S D0 D1 WE WCLK A0 A1 A2 A3 Virtex E XCV2000 has 160 blocks O0 O1 or RAM16X1D D WE A0 4096 bits per blocks 4K x 1 2K x 4 512 x 8 256 x 16 Use multiple blocks for larger memories WCLK SPO A1 A2 A3 Builds both single and true dual port RAMs DPRA0 DPO DPRA1 DPRA2 CORE Generator provides custom sized block RAMs DPRA3 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Lec6 11 Quickly generates optimized RAM implementation 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Lec6 12 Additional Application Shift Register Example Partition Placement and Route Idealized FPGA structure Each LUT can be configured as shift register Serial in serial out Example Schematic Circuit collection of gates and flipflops LUT D Q CE IN CE CLK Saves resources can use less than 16 FFs Faster no routing D Q CE Note CAD tools determine with CLB used as LUT RAM or shift register rather than up to designer LUT D Q CE OUT Circuit combinational logic must be covered by 4 input 1 output gates D Q CE DEPTH 3 0 2 11 03 Placement in general attempts to minimize wiring CS152 Kubiatowicz Lec6 13 UCB Spring 2004 TRISTATE BUSSES LONG LONG HEX HEX SINGLE HEX SWITCH MATRIX
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