CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design Continued Mar 1 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Recap Partition datapath into equal size chunks to minimize cycle time 10 levels of logic between latches Follow same 5 step method for designing real processor Control is specified by finite state digram 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Overview of Control Control may be designed using one of several initial representations The choice of sequence control and how logic is represented can then be determined independently the control can then be implemented with one of several methods using a structured logic technique Initial Representation Sequencing Control Logic Representation Implementation Technique 3 1 99 Finite State Diagram Microprogram Explicit Next State Microprogram counter Function Dispatch ROMs Logic Equations PLA hardwired control UCB Spring 1999 Truth Tables ROM microprogrammed control CS152 Kubiatowicz Recap Controller Design The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer Control reduces to programming this very simple device microprogramming sequencer control datapath control microinstruction micro PC 3 1 99 sequencer UCB Spring 1999 CS152 Kubiatowicz Recap Microprogram Control Specification PC 0000 0001 0001 0010 BEQ 0011 R 0100 0101 ORi 0110 0111 1000 LW 1001 1010 SW 1011 1100 3 1 99 Taken 0 1 x x x x x x x x x x x inc load inc zero zero inc zero inc zero inc inc zero inc zero Next IR PC Ops Exec Mem Write Back en sel A B Ex Sr ALU S R W M M R Wr Dst 1 1 1 0 1 0 1 1 1 1 1 1 0 1 fun 1 0 0 1 1 0 or 1 0 0 1 0 0 add 1 0 1 0 1 1 0 0 add 1 1 0 0 1 UCB Spring 1999 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topics Microprogramed control Administrivia Microprogram it yourself Exceptions 3 1 99 UCB Spring 1999 CS152 Kubiatowicz How Effectively are we utilizing our hardware IR Mem PC A R rs B R rt S A B R rd S PC PC 4 S A or ZX R rt S PC PC 4 S A SX S A SX M Mem S Mem S B R rd M PC PC 4 PC PC 4 PC PC 4 PC PC SX Example memory is used twice at different times Ave mem access per inst 1 Flw Fsw 1 3 if CPI is 4 8 imem utilization 1 4 8 dmem 0 3 4 8 We could reduce HW without hurting performance 3 1 99 extra control UCB Spring 1999 CS152 Kubiatowicz Princeton Organization A Bus B Bus next PC P C IR ZX SX Reg File A B S Mem W Bus Single memory for instruction and data access memory utilization 1 3 4 8 Sometimes muxes replaced with tri state buses Difference often depends on whether buses are internal to chip muxes or external tri state In this case our state diagram does not change several additional control signals must ensure each bus is only driven by one source on each cycle 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Alternative datapath book Multiple Cycle Datapath Miminizes Hardware 1 memory 1 adder PCWr 1 WrAdr 32 Din Dout 32 Rt 0 5 Rd Ra Rb busA Reg File Rw busW busB 32 1 1 Mux 0 Imm 16 32 2 Extend ExtOp 4 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 1999 Zero 32 1 Target ALU Out 1 32 Mux Ideal Memory Rt 5 32 0 0 Rs BrWr ALU Mux RAdr 32 3 1 99 ALUSelA RegWr Mux 0 Instruction Reg 32 32 RegDst 32 PC 32 PCSrc Mux PCWrCond Zero IorD MemWr IRWr ALUOp ALUSelB CS152 Kubiatowicz Our Controller FSM Spec IR MEM PC PC PC 4 0000 instruction fetch decode A R rs B R rt S A fun B 0100 ORi S A op ZX 0110 LW S A SX 1000 BEQ SW S A SX 1011 S A B 0010 Equal M MEM S 1001 R rd S 0101 3 1 99 R rt S 0111 MEM S B 1100 R rt M 1010 UCB Spring 1999 Equal PC PC SX 00 0011 Write back R type Memory Execute 0001 CS152 Kubiatowicz Microprogrammin g Control is the hard part of processor design Datapath is fairly regular and well organized Memory is highly regular Control is irregular and global Microprogramming A Particular Strategy for Implementing the Control Unit of a processor by programming at the level of register transfer operations Microarchitecture Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note IBM 360 Series first to distinguish between architecture organization Same instruction set across wide range of implementations each with different cost performance 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Sequencer based control unit Control Logic Multicycle Datapath Outputs Inputs 1 Adder Types of branching Set state to 0 Dispatch state 1 Use incremented state number State Reg Address Select Logic Opcode 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Macroinstruction Interpretation Main Memory ADD SUB AND DATA execution unit CPU User program plus Data this can change one of these is mapped into one of these AND microsequence control memory e g Fetch Calc Operand Addr Fetch Operand s Calculate Save Answer s 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Variations on Microprogramming Horizontal Microcode control field for each control point in the machine seq addr A mux B mux bus enables register enables Vertical Microcode compact microinstruction format for each class of microoperation local decode to generate all control points branch seq op add execute ALU op A B R memory mem op S D Horizontal Vertical 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Extreme Horizontal 3 1 N3 N2 N1 N0 1 bit for each loadable register enbMAR enbAC input select Incr PC ALU control Depending on bus organization many potential control combinations simply wrong i e implies transfers that can never happen at the same time Makes sense to encode fields to save ROM space Example mem to reg and ALU to reg should never happen simultaneously encode in single bit which is decoded rather than two separate bits NOTE the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction 3 1 99 UCB Spring 1999 CS152 Kubiatowicz More Vertical Format src dst D E C other control fields next states inputs D E C MUX Some of these may have nothing to do with registers Multiformat Microcode 6 1 3 0 cond 1 1 3 dst D E C 3 1 99 next address 3 src 3 alu Branch Jump Register Xfer Operation D E C UCB Spring 1999 CS152 Kubiatowicz Hybrid Control Not all …
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