CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design (Continued)RecapOverview of ControlRecap: Controller DesignRecap: Microprogram Control SpecificationThe Big Picture: Where are We Now?How Effectively are we utilizing our hardware?“Princeton” OrganizationAlternative datapath (book): Multiple Cycle DatapathOur Controller FSM SpecMicroprogrammingSequencer-based control unit“Macroinstruction” InterpretationVariations on MicroprogrammingExtreme HorizontalMore Vertical FormatHybrid ControlVax MicroinstructionsHorizontal vs. Vertical MicroprogrammingAdministrationDesigning a Microinstruction Set1&2) Start with list of control signals, grouped into fieldsStart with list of control signals, cont’d3) Microinstruction Format: unencoded vs. encoded fields4) Legend of Fields and Symbolic NamesMicroprogram it yourself!Slide 27Legacy Software and MicroprogrammingMicroprogramming Pros and ConsAn Alternative MultiCycle DataPathWhat about a 2-Bus Microarchitecture (datapath)?LoadExceptionsWhat happens to Instruction with Exception?Two Types of ExceptionsMIPS convention:Addressing the Exception HandlerSaving StateAdditions to MIPS ISA to support Exceptions?Recap: Details of Status registerBig Picture: user / system modesRecap: Details of Cause registerPrecise InterruptsHow Control Detects Exceptions in our FSDModification to the Control SpecificationSummarySummary: Microprogramming one inspiration for RISC3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.1CS 152 Computer Architecture and EngineeringLecture 10Multicycle Controller Design (Continued) Mar 1, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.2Recap°Partition datapath into equal size chunks to minimize cycle time•~10 levels of logic between latches°Follow same 5-step method for designing “real” processor°Control is specified by finite state digram3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.3Overview of Control°Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.Initial Representation Finite State Diagram MicroprogramSequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth TablesImplementation PLA ROM Technique“hardwired control” “microprogrammed control”3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.4Recap: Controller Design°The state digrams that arise define the controller for an instruction set processor are highly structured°Use this structure to construct a simple “microsequencer” °Control reduces to programming this very simple device•microprogrammingsequencercontroldatapath controlmicro-PCsequencermicroinstruction ()3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.5Recap: Microprogram Control Specification0000 ? inc 10001 0 load0001 1 inc0010 x zero 1 10011 x zero 1 00100 x inc 0 1 fun 10101 x zero 1 0 0 1 10110 x inc 0 0 or 10111 x zero 1 0 0 1 01000 x inc 1 0 add 11001 x inc 1 0 11010 x zero 1 0 1 1 01011 x inc 1 0 add 11100 x zero 1 0 0 1 µPC Taken Next IR PC Ops Exec Mem Write-Backen sel A B Ex Sr ALU S R W M M-R Wr DstR:ORi:LW:SW:BEQ3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.6The Big Picture: Where are We Now? °The Five Classic Components of a Computer°Today’s Topics: •Microprogramed control•Administrivia•Microprogram it yourself•ExceptionsControlDatapathMemoryProcessorInputOutput3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.7How Effectively are we utilizing our hardware?°Example: memory is used twice, at different times•Ave mem access per inst = 1 + Flw + Fsw ~ 1.3•if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8°We could reduce HW without hurting performance•extra controlIR <- Mem[PC]A <- R[rs]; B<– R[rt]S <– A + BR[rd] <– S;PC <– PC+4;S <– A + SXM <– Mem[S]R[rd] <– M;PC <– PC+4;S <– A or ZXR[rt] <– S;PC <– PC+4;S <– A + SXMem[S] <- BPC <– PC+4;PC < PC+4; PC < PC+SX;3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.8“Princeton” Organization°Single memory for instruction and data access •memory utilization -> 1.3/4.8°Sometimes, muxes replaced with tri-state buses•Difference often depends on whether buses are internal to chip (muxes) or external (tri-state)°In this case our state diagram does not change•several additional control signals•must ensure each bus is only driven by one source on each cycleRegFileABA-BusB BusIRSW-BusPCnextPCZX SXMem3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.9Alternative datapath (book): Multiple Cycle Datapath°Miminizes Hardware: 1 memory, 1 adderIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControlInstruction Reg32IRWr32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux10Target32ZeroZeroPCWrCond PCSrc BrWr32IorDALU Out3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.10Our Controller FSM SpecIR <= MEM[PC]PC <= PC + 4R-typeA <= R[rs]B <= R[rt]S <= A fun BR[rd] <= SS <= A op ZXR[rt] <= SORiS <= A + SXR[rt] <= MM <= MEM[S]LWS <= A + SXMEM[S] <= BSW“instruction fetch”“decode”ExecuteMemoryWrite-back00000001010001010110011110001001101010111100~EqualEqualBEQPC <= PC + SX || 0000100011S <= A - B3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.11Microprogramming°Control is the hard part of processor design° Datapath is fairly regular and well-organized° Memory is highly regular° Control is irregular and globalMicroprogramming:-- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operationsMicroarchitecture:-- Logical structure and functional capabilities of the hardware as seen by the microprogrammerHistorical Note:IBM 360 Series first to distinguish between architecture & organizationSame instruction set across wide range of implementations, each with different cost/performance3/1/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec10.12Sequencer-based control unitOpcodeState RegInputsOutputsControl LogicMulticycleDatapath1Address Select
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