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Berkeley COMPSCI 152 - Lecture 15 - Out-of-Order Memory, Complex Superscalars Review

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CS 152 Computer Architecture and Engineering Lecture 15 - Out-of-Order Memory, Complex Superscalars ReviewReview of Last 3 LecturesPhases of Instruction ExecutionIn-Order PipelineException Handling (In-Order Five-Stage Pipeline)In-Order Superscalar PipelineOut-of-Order IssueRegister RenamingOut-of-Order Execution Pipeline“Data in ROB” Design (HP PA8000, Pentium Pro, Core2Duo)Unified Physical Register File (MIPS R10K, Alpha 21264, Pentium 4)PowerPoint PresentationCS152 AdministriviaMemory DependenciesIn-Order Memory QueueConservative O-o-O Load ExecutionAddress SpeculationMemory Dependence Prediction (Alpha 21264)Speculative Loads / StoresSpeculative Store BufferSlide 21Slide 22Instruction Flow in Unified Physical Register File PipelineMemory InstructionsIssue StageExecute StageCommit StageAcknowledgementsCS 152 Computer Architecture and Engineering Lecture 15 - Out-of-Order Memory, Complex Superscalars ReviewKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs1523/31/2009 CS152-Spring’092Review of Last 3 Lectures3/31/2009 CS152-Spring’093Fetch: Instruction bits retrieved from cache.Phases of Instruction ExecutionI-cacheFetch BufferIssueBufferFunc.UnitsArch.StateExecute: Instructions and operands sent to execution units. When execution completes, all results and exception flags are available.Decode: Instructions decoded, registers renamed, placed in appropriate issue buffer.ResultBufferCommit: Instruction irrevocably updates architectural state.PC3/31/2009 CS152-Spring’094In-Order PipelineIF ID WBALU MemFaddFmulFdivIssueInstructions pass through issue stage and enter execution in-order.May complete out-of-order, but must commit in-order.3/31/2009 CS152-Spring’095Exception Handling(In-Order Five-Stage Pipeline)• Hold exception flags in pipeline until commit point (M stage)• Exceptions in earlier pipe stages override later exceptions• Inject external interrupts at commit point (override others)• If exception at commit: update Cause and EPC registers, kill all stages, inject handler PC into fetch stageAsynchronous InterruptsExcDPCDPCInst. MemDDecodeE MData MemW+ExcEPCEExcMPCMCauseEPCKill D StageKill F StageKill E StageIllegal OpcodeOverflowData Addr ExceptPC Address ExceptionsKill WritebackSelect Handler PCCommit Point3/31/2009 CS152-Spring’096In-Order Superscalar Pipeline•Fetch two instructions per cycle; issue both simultaneously if one is integer/memory and other is floating point•Inexpensive way of increasing throughput, examples include Alpha 21064 (1992) & MIPS R5000 series (1996)•Same idea can be extended to wider issue by duplicating functional units (e.g. 4-issue UltraSPARC) but regfile ports and bypassing costs grow quicklyCommit Point2PCInst. MemDDualDecodeX1 X2Data MemW+GPRsX2 WFAddX3X3FPRsX1X2FMulX3X2FDiv X3Unpipelined divider3/31/2009 CS152-Spring’097Out-of-Order Issue•Issue stage buffer holds multiple instructions waiting to issue.•Decode adds next instruction to buffer if there is space and the instruction does not cause a WAR or WAW hazard.–Note: WAR possible again because issue is out-of-order (WAR not possible with in-order issue and latching of input operands at functional unit)•Any instruction in buffer whose RAW hazards are satisfied can be issued (for now at most one dispatch per cycle). On a write back (WB), new instructions may get enabled.IF ID WBALU MemFaddFmulIssue3/31/2009 CS152-Spring’098Register Renaming•Decode does register renaming and adds instructions to the issue stage reorder buffer (ROB)  renaming makes WAR or WAW hazards impossible•Any instruction in ROB whose RAW hazards have been satisfied can be dispatched.  Out-of-order or dataflow executionIF ID WBALU MemFaddFmulIssue3/31/2009 CS152-Spring’099Out-of-Order Execution Pipeline• Instructions fetched and decoded into instruction reorder buffer in-order• Execution is out-of-order (  out-of-order completion)• Commit (write-back to architectural state, i.e., regfile & memory), is in-orderTemporary storage needed in ROB to hold results before commitFetch DecodeExecuteCommitReorder BufferIn-order In-orderOut-of-orderKillKillKillException?Inject handler PC3/31/2009 CS152-Spring’0910“Data in ROB” Design(HP PA8000, Pentium Pro, Core2Duo)• On dispatch into ROB, ready sources can be in regfile or in ROB dest (copied into src1/src2 if ready before dispatch)• On completion, write to dest field and broadcast to src fields.• On issue, read from ROB src fieldsRegister Fileholds only committed stateReorderbufferLoad UnitFU FUFUStore Unit< t, result >t1t2..tnIns# use exec op p1 src1 p2 src2 pd dest dataCommit3/31/2009 CS152-Spring’0911Unified Physical Register File(MIPS R10K, Alpha 21264, Pentium 4)• One regfile for both committed and speculative values (no data in ROB)• During decode, instruction result allocated new physical register, source regs translated to physical regs through rename table• Instruction reads data from regfile at start of execute (not in decode)• Write-back updates reg. busy bits on instructions in ROB (assoc. search)• Snapshots of rename table taken at every branch to recover mispredicts• On exception, renaming undone in reverse order of issue (MIPS R10000)Rename Tabler1 tir2 tjFUFUStore Unit< t, result >FULoad UnitFUt1t2.tnRegFileSnapshots for mispredict recovery(ROB not shown)3/31/2009 CS152-Spring’0912Pipeline Design with Physical RegfileFetchDecode & RenameReorder BufferPCBranchPredictionUpdate predictorsCommitBranchResolutionBranchUnitALUMEMStore BufferD$ExecuteIn-OrderIn-OrderOut-of-OrderPhysical Reg. Filekillkillkillkill3/31/2009 CS152-Spring’0913CS152 Administrivia•Quiz 4, Tuesday April 7, Complex Pipelining•Quiz 5 and 6 moved back one class:–Quiz 5, Thursday April 23–Quiz 6, Thursday May 7•Also, PS/Lab 5/6 moved back one class3/31/2009 CS152-Spring’0914Memory Dependenciesst r1, (r2)ld r3, (r4)When can we execute the load?3/31/2009 CS152-Spring’0915In-Order Memory Queue•Execute all loads and stores in program order=> Load and store cannot leave ROB for execution until all previous loads and stores have completed execution•Can still execute loads and stores speculatively, and out-of-order with respect to other instructions•Need a structure to handle memory ordering…3/31/2009 CS152-Spring’0916Conservative O-o-O


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Berkeley COMPSCI 152 - Lecture 15 - Out-of-Order Memory, Complex Superscalars Review

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