Recap Making address translation practical TLB CS152 Computer Architecture and Engineering Lecture 24 Virtual memory memory acts like a cache for the disk Page table maps virtual page numbers to physical frames Translation Look aside Buffer TLB is a cache translations Buses continued Disk IO Queueing Theory virtual address Virtual Address Space page Physical Memory Space off Page Table 2 0 April 30 2003 John Kubiatowicz www cs berkeley edu kubitron 1 3 physical address lecture slides http inst eecs berkeley edu cs152 TLB page off frame page 2 2 0 5 4 30 03 CS152 Kubiatowicz Lec24 1 UCB Spring 2003 Recap Overlapped TLB Cache Access 4 30 03 CS152 Kubiatowicz Lec24 2 UCB Spring 2003 Recap A Three Bus System backside cache If we do this in parallel we have to be careful however Processor Memory Bus Processor Backside Cache bus assoc lookup 32 index TLB 4K Cache 10 2 disp 00 20 page 1K Bus Adaptor Bus Adaptor I O Bus L2 Cache Bus Adaptor I O Bus 4 bytes Hit Miss FN Memory FN Data Hit Miss A small number of backplane buses tap into the processor memory bus Processor memory bus is only used for processor memory traffic I O buses are connected to the backplane bus Advantage loading on the processor bus is greatly reduced What if cache size is increased to 8KB 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 3 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 4 Recap Main components of Intel Chipset Pentium II III Synchronous and Asynchronous Bus Synchronous Bus Includes a clock in the control lines Northbridge Handles memory A fixed protocol relative to the clock Advantage little logic and very fast Disadvantages Graphics Southbridge I O PCI bus Disk controllers USB controlers Asynchronous Bus It is not clocked It can accommodate a wide range of devices Audio Serial I O Interrupt controller It can be lengthened without worrying about clock skew It requires a handshaking protocol Timers 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 5 4 30 03 Simple Synchronous Protocol BReq BG BG Data R W Address Cmd Addr Data1 CS152 Kubiatowicz Lec24 6 UCB Spring 2003 Typical Synchronous Protocol BReq R W Address Every device on the bus must run at the same clock rate To avoid clock skew they cannot be long if they are fast Cmd Addr Data2 Wait Data Even memory busses are more complex than this memory slave may take time to respond Data1 Data1 Data2 Slave indicates when it is prepared for data xfer it may need to control data rate Actual transfer goes at bus rate 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 7 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 8 Asynchronous Write Transaction Asynchronous Read Transaction Write Transaction Address Master Asserts Address Data Master Asserts Data Address Next Address Master Asserts Address Data Next Address Slave Data Read Read Req Req Ack Ack t0 t0 t1 t2 t3 t4 t5 t0 Master has obtained control and asserts address direction data Waits a specified amount of time for slaves to decode target t1 t2 t3 t4 t5 t0 Master has obtained control and asserts address direction data Waits a specified amount of time for slaves to decode target t1 Master asserts request line t1 Master asserts request line t2 Slave asserts ack indicating data received t2 Slave asserts ack indicating ready to transmit data t3 Master releases req t3 Master releases req data received t4 Slave releases ack t4 Slave releases ack 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 9 Multiple Potential Bus Masters the Need for Arbitration 4 30 03 CS152 Kubiatowicz Lec24 10 UCB Spring 2003 Arbitration Obtaining Access to the Bus Bus arbitration scheme Control Master initiates requests A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus Bus Master Bus arbitration schemes usually try to balance two factors Data can go either way Bus Slave One of the most important issues in bus design How is the bus reserved by a device that wishes to use it Bus priority the highest priority device should be serviced first Fairness Even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four broad classes Daisy chain arbitration Centralized parallel arbitration Distributed arbitration by self selection each device wanting the bus places a code indicating its identity on the bus Distributed arbitration by collision detection Each device just goes for it Problems found after the fact Chaos is avoided by a master slave arrangement Only the bus master can control access to the bus It initiates and controls all bus requests A slave responds to read and write requests The simplest system Processor is the only bus master All bus requests must be controlled by the processor Major drawback the processor is involved in every transaction 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 11 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 12 The Daisy Chain Bus Arbitrations Scheme Device 1 Highest Priority Grant Device N Lowest Priority Device 2 Grant Centralized Parallel Arbitration Device 1 Grant Grant Release Bus Arbiter Device 2 Device N Req Bus Arbiter Request wired OR Advantage simple Disadvantages Cannot assure fairness A low priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 13 Increasing the Bus Bandwidth 4 30 03 UCB Spring 2003 CS152 Kubiatowicz Lec24 14 Increasing Transaction Rate on Multimaster Bus Separate versus multiplexed address and data lines Overlapped arbitration Address and data can be transmitted in one bus cycle if separate address and data lines are available perform arbitration for next transaction during current transaction Cost a more bus lines b increased complexity Bus parking master can holds onto bus and performs multiple transactions as long as no other master makes request Data bus width By increasing the width of the data bus transfers of multiple words require fewer bus cycles Example SPARCstation 20 s memory bus is 128 bit wide Overlapped address data phases prev slide requires one of the above techniques Cost more bus lines Split phase or packet switched bus Block transfers completely separate address and data phases arbitrate separately for each address phase yield a tag which is matched with data phase Allow the bus to transfer multiple words in back to back bus cycles Only one address
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