February 23, 2010 CS152, Spring 2010 CS 152 Computer Architecture and Engineering Lecture 10 - Virtual Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!http://inst.eecs.berkeley.edu/~cs152!February 23, 2010 CS152, Spring 2010 Last time in Lecture 9 • Protection and translation required for multiprogramming – Base and bounds, early simple scheme • Page-based translation and protection avoids need for memory compaction, easy allocation by OS – But need to indirect in large page table on every access • Address spaces accessed sparsely – Can use multi-level page table to hold translation/protection information • Address space access with locality – Can use “translation lookaside buffer” (TLB) to cache address translations (sometimes known as address translation cache) – Still have to walk page tables on TLB miss, can be hardware or software talk • Virtual memory uses DRAM as a “cache” of disk memory, allows very cheap main memoryFebruary 23, 2010 CS152, Spring 2010 Modern Virtual Memory Systems Illusion of a large, private, uniform store Protection & Privacy several users, each with their private address space and one or more shared address spaces page table ! name space Demand Paging Provides the ability to run programs larger than the primary memory Hides differences in machine configurations The price is address translation on each memory reference OS useri Primary Memory Swapping Store VA PA mapping TLB February 23, 2010 CS152, Spring 2010 Hierarchical Page Table Level 1 Page Table Level 2 Page Tables Data Pages page in primary memory page in secondary memory Root of the Current Page Table p1 offset p2 Virtual Address (Processor Register) PTE of a nonexistent page p1 p2 offset 0 11 12 21 22 31 10-bit L1 index 10-bit L2 indexFebruary 23, 2010 CS152, Spring 2010 Address Translation & Protection • !Every instruction and data access needs address translation and protection checks A good VM design needs to be fast (~ one cycle) and space efficient Physical Address Virtual Address Address Translation Virtual Page No. (VPN) offset Physical Page No. (PPN) offset Protection Check Exception? Kernel/User Mode Read/Write February 23, 2010 CS152, Spring 2010 Translation Lookaside Buffers Address translation is very expensive! In a two-level page table, each reference becomes several memory accesses Solution: Cache translations in TLB TLB hit " Single Cycle Translation TLB miss " Page Table Walk to refill VPN offset V R W D tag PPN physical address PPN offset virtual address hit? (VPN = virtual page number) (PPN = physical page number)February 23, 2010 CS152, Spring 2010 Handling a TLB Miss Software (MIPS, Alpha) TLB miss causes an exception and the operating system walks the page tables and reloads TLB. A privileged “untranslated” addressing mode used for walk Hardware (SPARC v8, x86, PowerPC) A memory management unit (MMU) walks the page tables and reloads the TLB If a missing (data or PT) page is encountered during the TLB reloading, MMU gives up and signals a Page-Fault exception for the original instruction February 23, 2010 CS152, Spring 2010 Translation for Page Tables • Can references to page tables cause TLB misses? • Can this go on forever? User Page Table (in virtual space) Data Pages User PTE Base System Page Table (in physical space) System PTE BaseFebruary 23, 2010 CS152, Spring 2010 Variable-Sized Page Support Level 1 Page Table Level 2 Page Tables Data Pages page in primary memory large page in primary memory page in secondary memory PTE of a nonexistent page Root of the Current Page Table p1 offset p2 Virtual Address (Processor Register) p1 p2 offset 0 11 12 21 22 31 10-bit L1 index 10-bit L2 index February 23, 2010 CS152, Spring 2010 Variable-Size Page TLB Some systems support multiple page sizes. VPN offset physical address PPN offset virtual address hit? V R W D Tag PPN LFebruary 23, 2010 CS152, Spring 2010 Address Translation: putting it all together Virtual Address TLB Lookup Page Table Walk Update TLB Page Fault (OS loads page) Protection Check Physical Address (to cache) miss hit the page is # memory $ memory denied permitted Protection Fault hardware hardware or software software SEGFAULT Restart instruction February 23, 2010 CS152, Spring 2010 Address Translation in CPU Pipeline • Software handlers need restartable exception on page fault or protection violation • Handling a TLB miss needs a hardware or software mechanism to refill TLB • Need mechanisms to cope with the additional latency of a TLB: – slow down the clock – pipeline the TLB and cache access – virtual address caches – parallel TLB/cache access PC Inst TLB Inst. Cache D Decode E M Data TLB Data Cache W + TLB miss? Page Fault? Protection violation? TLB miss? Page Fault? Protection violation?February 23, 2010 CS152, Spring 2010 Virtual Address Caches • one-step process in case of a hit (+) • cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) • aliasing problems due to the sharing of pages (-) • maintaining cache coherence (-) (see later in course) CPU Physical Cache TLB Primary Memory VA PA Alternative: place the cache before the TLB CPU VA (StrongARM) Virtual Cache PA TLB Primary Memory February 23, 2010 CS152, Spring 2010 Aliasing in Virtual-Address Caches VA1 VA2 Page Table Data Pages PA VA1 VA2 1st Copy of Data at PA 2nd Copy of Data at PA Tag Data Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solution: Disallow aliases to coexist in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct-mapped cache (early SPARCs)February 23, 2010 CS152, Spring 2010 CS152 Administrivia • Quiz 2: Tuesday March 3. Covers Lectures 6-8, PS2, and Lab 2 February 23, 2010 CS152, Spring 2010 Concurrent Access to TLB & Cache Index L is available without consulting the TLB " cache and TLB accesses can begin simultaneously Tag comparison is made after both accesses are completed Cases: L + b = k, L + b < k, L + b
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