CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design Continued October 3 2001 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 10 03 01 UCB Fall 2001 CS152 Kubiatowicz 10 03 01 Operand Fetch Instruction Fetch PC Next PC UCB Fall 2001 Exec Reg File Result Store Data Mem Mem Access MemWr RegDst RegWr MemRd MemWr ALUctr ALUSrc ExtOp Equal nPC sel Partitioning the CPI 1 Datapath Add registers between smallest steps CS152 Kubiatowicz 10 03 01 ExtOp Equal B UCB Fall 2001 S Reg File RegDst RegWr MemToReg MemRd MemWr ALUctr Ext ALUSrc ALU A Result Store Reg File Mem Access IR nPC sel E Data Mem Operand Fetch Instruction Fetch PC Next PC Recap Example Multicycle Datapath M Critical Path CS152 Kubiatowicz Recap FSM specification instruction fetch IR MEM PC 0000 decode A R rs B R rt S A fun B 0100 ORi S A or ZX 0110 LW S A SX 1000 M MEM S 1001 SW BEQ S A SX 1011 MEM S B PC PC 4 R rd S R rt S R rt M PC PC 4 PC PC 4 PC PC 4 0101 10 03 01 0111 1010 UCB Fall 2001 1100 PC Next PC 0011 Write back Memory R type Execute 0001 CS152 Kubiatowicz Sequencer based control unit Statemachine Control Logic Multicycle Datapath Outputs Inputs 1 Adder Types of branching Set state to 0 Dispatch state 1 Use incremented state number State Reg Address Select Logic Opcode 10 03 01 UCB Fall 2001 CS152 Kubiatowicz Recap Micro controller Design The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer Each state in previous diagram becomes a microinstruction Microinstructions often taken sequentially Control reduces to programming this device sequencer control datapath control microinstruction micro PC 10 03 01 sequencer UCB Fall 2001 CS152 Kubiatowicz Recap Specific Sequencer from last lecture Sequencer based control unit from last lecture Called microPC or PC vs state register Control Value Effect 00 Next address 0 01 Next address dispatch ROM 10 Next address address 1 1 Adder ROM 10 03 01 R type BEQ ori LW SW 000000 000100 001101 100011 101011 0100 0011 0110 1000 1011 Address Select Logic UCB Fall 2001 microPC Mux 2 1 0 0 ROM Opcode CS152 Kubiatowicz Recap Microprogram Control Specification PC 0000 0001 0001 0010 BEQ 0011 R 0100 0101 ORi 0110 0111 1000 LW 1001 1010 SW 1011 1100 10 03 01 Taken 0 1 x x x x x x x x x x x inc load inc zero zero inc zero inc zero inc inc zero inc zero Next IR PC Ops Exec Mem Write Back en sel A B Ex Sr ALU S R W M M R Wr Dst 1 1 1 0 1 0 1 1 1 1 1 1 0 1 fun 1 0 0 1 1 0 or 1 0 0 1 0 0 add 1 0 1 0 1 1 0 0 add 1 1 0 0 1 UCB Fall 2001 CS152 Kubiatowicz Recap Overview of Control Control may be designed using one of several initial representations The choice of sequence control and how logic is represented can then be determined independently the control can then be implemented with one of several methods using a structured logic technique Initial Representation Sequencing Control Logic Representation Implementation Technique 10 03 01 Finite State Diagram Microprogram Explicit Next State Microprogram counter Function Dispatch ROMs Logic Equations PLA hardwired control UCB Fall 2001 Truth Tables ROM microprogrammed control CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topics Microprogramed control Administrivia Microprogram it yourself Exceptions 10 03 01 UCB Fall 2001 CS152 Kubiatowicz Microprogramming Maurice Wilkes Control is the hard part of processor design Datapath is fairly regular and well organized Memory is highly regular Control is irregular and global Microprogramming A Particular Strategy for Implementing the Control Unit of a processor by programming at the level of register transfer operations Microarchitecture Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note IBM 360 Series first to distinguish between architecture organization Same instruction set across wide range of implementations each with different cost performance 10 03 01 UCB Fall 2001 CS152 Kubiatowicz Macroinstruction Interpretation Main Memory ADD SUB AND DATA execution unit CPU User program plus Data this can change one of these is mapped into one of these AND microsequence control memory e g Fetch Calc Operand Addr Fetch Operand s Calculate Save Answer s 10 03 01 UCB Fall 2001 CS152 Kubiatowicz Variations on Microprogramming Horizontal Microcode control field for each control point in the machine seq addr A mux B mux bus enables register enables Vertical Microcode compact microinstruction format for each class of microoperation local decode to generate all control points remember ALU branch seq op add execute ALU op A B R memory mem op S D Horizontal Vertical 10 03 01 UCB Fall 2001 CS152 Kubiatowicz Extreme Horizontal 3 1 N3 N2 N1 N0 1 bit for each loadable register enbMAR enbAC input select Incr PC ALU control Depending on bus organization many potential control combinations simply wrong i e implies transfers that can never happen at the same time Makes sense to encode fields to save ROM space Example mem to reg and ALU to reg should never happen simultaneously encode in single bit which is decoded rather than two separate bits NOTE the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction 10 03 01 UCB Fall 2001 CS152 Kubiatowicz More Vertical Format src dst D E C other control fields next states inputs D E C MUX Some of these may have nothing to do with registers Multiformat Microcode 6 1 3 0 cond 1 1 3 dst D E C 10 03 01 next address 3 src 3 alu Branch Jump Register Xfer Operation D E C UCB Fall 2001 CS152 Kubiatowicz Hybrid Control Not all critical control information is derived from control logic E g Instruction Register IR contains useful control information such as register sources destinations opcodes etc enable signals from control IR op to control 10 03 01 R S 1 R S 2 R D D E C D E C D E C rs1 rs2 Register File rd UCB Fall 2001 CS152 Kubiatowicz Vax Microinstructions VAX Microarchitecture 96 bit control store 30 fields 4096 instructions for VAX ISA encodes concurrently executable microoperations 95 87 84 USHF 001 left 010 right 101 left3 68 65 63 11 UALU USUB 010 A B 1 100 A B 1 ALU Control 0 UJMP 00 Nop 01 CALL 10 RTN Jump Address Subroutine Control ALU Shifter Control
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