1University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2004 John KubiatowiczHomework Quiz (HW #3) March 3rd, 2004 CS152 Computer Architecture and Engineering This quiz covers one of the problems from homework #3. Good Luck! Your Name: SID Number: Discussion Section: Total:2Figure 1: A multicycle data path Figure 1 shows the multicycle datapath from the book. In your homework, you implemented the bcp instruction, which copied a block of words from one location in memory to another. In this problem, we will implement something simpler, namely the block zero (bzero) instruction: bzero $t1,$t2 ⇒ {0 ⇒ mem[t1], 0 ⇒ mem[t1+4], …, 0 ⇒ mem[t1+(t2-1)*4]} This instruction zeros a block of memory of size $t2 words, starting at the address in register $t1. The coding of this instruction is as follows: $t1 is in the RT field, $t2 is in the RS field. Problem 1a: What changes are required to the datapath for this instruction? Assume that you can use a 30-bit counter with separate load and decrement signals. Only redraw/describe the affected parts of the datapath. Do not change the register file. Big hint: count*4 can be added to a base address, so zero elements of the vector starting at the end. IdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCondPCSrc32IorDMem Data RegALU OutBA3 Field Name Values For Field Function of Field Add ALU Adds Sub ALU subtracts Func ALU does function code (Inst[5:0]) ALU Or ALU does logical OR PC PC ⇒ 1st ALU input SRC1 rs R[rs] ⇒1st ALU input 4 4 ⇒ 2nd ALU input rt R[rt] ⇒ 2nd ALU input Extend sign ext imm16 (Inst[15:0]) ⇒ 2nd ALU input Extend0 zero ext imm16 (Inst[15:0]) ⇒ 2nd ALU input SRC2 ExtShft 2nd ALU input = sign extended imm16 << 2 rd-ALU ALUout ⇒ R[rd] rt-ALU ALUout ⇒ R[rt] ALU Dest rt-Mem Mem input ⇒ R[rt] Read-PC Read Memory using the PC for the address Read-ALU Read Memory using the ALUout register for the address Memory Write-ALU Write Memory using the ALUout register for the address MemReg IR Mem input ⇒ IR ALU ALU value ⇒ PCibm PC Write ALUoutCond If ALU Zero is true, then ALUout ⇒ PC Seq Go to next sequential microinstruction Fetch Go to the first microinstruction Sequence Dispatch Dispatch using ROM Label ALU SRC1 SRC2 ALUDest Memory MemReg PCWrite Sequence Fetch Add PC 4 ReadPC IR ALU Seq Dispatch Add PC ExtShft Dispatch SW add rs rt Seq Write-ALU Fetch Problem 1b: Above, we show the microcode assembly-language and the microcode for the store word(SW) instruction. What changes are needed to the microcode assembly language to support the bzero instruction? Hint: something will be added to the Sequence field! Problem 1c: Write complete microcode for bzero, including the fetch and dispatch cycles. Be careful not to make changes that would interfere with the other instructions. You shouldn’t need more than 5 or 6 total instructions (including fetch and
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