University of California Berkeley College of Engineering Computer Science Division EECS Spring 2004 John Kubiatowicz Homework Quiz HW 3 March 3rd 2004 CS152 Computer Architecture and Engineering This quiz covers one of the problems from homework 3 Good Luck Your Name SID Number Discussion Section Total 1 PCWr 32 Rd busA A Rb Reg File Rw busW busB 1 1 Mux 0 Extend Imm 16 ExtOp 2 32 32 32 0 1 32 32 2 3 32 MemtoReg Zero 1 4 B 0 ALU Out 32 Ra 32 ALU WrAdr 32 Din Dout 5 Rt 0 Mux Ideal Memory 1 5 32 Rt Mem Data Reg Mux RAdr 0 Rs 1 Mux ALUSelA RegWr Mux 0 Instruction Reg 32 32 RegDst 32 PC 32 PCSrc PCWrCond Zero IorD MemWr IRWr ALU Control ALUOp ALUSelB Figure 1 A multicycle data path Figure 1 shows the multicycle datapath from the book In your homework you implemented the bcp instruction which copied a block of words from one location in memory to another In this problem we will implement something simpler namely the block zero bzero instruction bzero t1 t2 0 mem t1 0 mem t1 4 0 mem t1 t2 1 4 This instruction zeros a block of memory of size t2 words starting at the address in register t1 The coding of this instruction is as follows t1 is in the RT field t2 is in the RS field Problem 1a What changes are required to the datapath for this instruction Assume that you can use a 30 bit counter with separate load and decrement signals Only redraw describe the affected parts of the datapath Do not change the register file Big hint count 4 can be added to a base address so zero elements of the vector starting at the end 2 Field Name ALU SRC1 SRC2 ALU Dest Memory MemReg PC Write Sequence Label Fetch Dispatch SW Values For Field Add Sub Func Or PC rs 4 rt Extend Extend0 ExtShft rd ALU rt ALU rt Mem Read PC Read ALU Write ALU IR ALU ALUoutCond Seq Fetch Dispatch ALU Add Add SRC1 PC PC SRC2 4 ExtShft add rs rt Function of Field ALU Adds ALU subtracts ALU does function code Inst 5 0 ALU does logical OR PC 1st ALU input R rs 1st ALU input 4 2nd ALU input R rt 2nd ALU input sign ext imm16 Inst 15 0 2nd ALU input zero ext imm16 Inst 15 0 2nd ALU input 2nd ALU input sign extended imm16 2 ALUout R rd ALUout R rt Mem input R rt Read Memory using the PC for the address Read Memory using the ALUout register for the address Write Memory using the ALUout register for the address Mem input IR ALU value PCibm If ALU Zero is true then ALUout PC Go to next sequential microinstruction Go to the first microinstruction Dispatch using ROM ALUDest Memory ReadPC Write ALU MemReg IR PCWrite ALU Sequence Seq Dispatch Seq Fetch Problem 1b Above we show the microcode assembly language and the microcode for the store word SW instruction What changes are needed to the microcode assembly language to support the bzero instruction Hint something will be added to the Sequence field Problem 1c Write complete microcode for bzero including the fetch and dispatch cycles Be careful not to make changes that would interfere with the other instructions You shouldn t need more than 5 or 6 total instructions including fetch and dispatch 3
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